Ho-Youb Cho

A 32Gb MLC NAND flash memory with V th margin-expanding schemes in 26nm CMOS

As the NAND flash memory market grows rapidly due to various applications, such as USB devices, MP3 players, SSDs, cellular phones, and cameras, there is a requirement for high-density and low-cost devices. Two different approaches to meet these requirements are increasing data per cell and area scaling. 3b/cell or 4b/cell NAND flash memories were introduced as an effective way to lower cost [1,2]. However, these devices suffer from program performance degradation since tighter Vth distribution is required. On the other hand, area scaling is a candidate to achieve low cost while maintaining high program performance even though there are several hurdles to overcome, such as FG coupling and charge retention [3]. As the cell size gets smaller, the Vth distribution widens and the erase-write cycling margin is decreased by the floating-gate coupling ratio [4].