Hock Koon Lee

Phase change random access memory cell with superlattice-like structure

A superlattice-like structure (SLL) incorporating two nonpromising phase change materials was applied to phase change random access memory (PCRAM) cell. A properly designed SLL structure could balance both the phase change speed and stability of a PCRAM. Moreover, SLL PCRAM cells exhibited lower programming current and fast working time of 5ns. The main reason for the excellent performances is due to the much lower thermal conductivity of the SLL material compared to that of bulk materials. The thermal conductivity of eight SLL layers cycle was found to be smaller than 30% of that of single layer material.

Role of Ge Switch in Phase Transition: Approach using Atomically Controlled GeTe/Sb2Te3 Superlattice

Germanium–antimony–tellurite (GST) is a very attractive material not only for rewritable optical media but also for realizing solid state devices. Recently, the study of the switching mechanism between the amorphous and crystal states has actively been carried out experimentally and theoretically. Now, the role of the flip-flop transition of a Ge atom in a distorted simple-cubic unit cell is the center of discussion. Turning our viewpoint towards a much wider region beyond a unit cell, we can understand that GeSbTe consists of two units: one is a Sb2Te3 layer and the other is a Ge2Te2 layer. On the based of this simple model, we fabricated the superlattice of GST alloys and estimated their thermal properties by differential scanning calorimetry (DSC). In this paper, we discuss the proof of the Ge switch on the basis of thermo-histories.

A new silane-ammonia surface passivation technology for realizing inversion-type surface-channel GaAs N-MOSFET with 160 nm gate length and high-quality metal-gate/high-k dielectric stack

We report a novel surface passivation technology employing a silane-ammonia gas mixture to realize very high quality high-k gate dielectric on GaAs. This technology eliminates the poor quality native oxide while forming an ultrathin silicon oxynitride (SiOxNy) interfacial passivation layer between the high-k dielectric and the GaAs surface. Interface state density Dit of about 1 times 1011 eV-1 cm-2 was achieved, which is the lowest reported value for a high-k dielectric formed on GaAs by CVD, ALD, or PVD techniques. This enables the formation of high quality gate stack on GaAs for high performance CMOS applications. We also realized the smallest reported (160 nm gate length) inversion-type enhancement-mode surface channel GaAs MOSFET. The surface-channel GaAs MOSFETs in this work has demonstrated one of the highest peak electron mobility of ~2100 cm2/Vmiddots. The lowest reported subthreshold swing (~100 mV/decade) for surface-channel GaAs MOSFETs was also achieved for devices with longer gate length. Extensive bias-temperature instability (BTI) characterization was performed to evaluate the reliability of the gate stack.

Integrated Analysis and Design of Phase-Change Random Access Memory (PCRAM) Cells

An integrated software for analysis and design of PCRAM cells has been developed. The research focuses on the discussion on electric-thermal -mechanical analyses. The software involves in the materials, geometrical and layer structure design and electric pulse strategy. It aims to provide a powerful tool for structure optimization and failure analysis of PCRAM cells.

Study of Phase Change Random Access Memory (PCRAM) at the Nano-Scale

In this paper, phase change random access memory (PCRAM) cells at the nano-scale was studied. A hybrid patterning process integrating with electron beam lithography (EBL) and optical lithography was used to fabricate nano-PCRAM cell. PCRAM cells with different feature sizes ranging from 40 nm to 200 nm have been fabricated and tested by an in-house developed tester which was capable of generation of pulse with short width. Electrical testing including programming current and speed have been conducted on the nano-cells. The resistance-current curves have shown a good scaling effect on the programming current against the cell size. Besides the current reduction, it was found that nano-PCRAM cells have shown an improved programming speed when its size reduces. RESET speed as fast as 2 ns was achieved for PCRAM cell with 45 nm. The improved speed was possible attributed to the nano-size effect due to the increasing contribution of the interfaces.

Investigations on nonvolatile and nonrotational phase change random access memory

In this work, phase change random access memory (PCRAM) was studied theoretically and experimentally. Phase change materials were deposited and their physical parameters were measured. A simulation and design software for PCRAM was developed based on multidisciplinary theories including electrodynamics, thermal conduction, crystallization kinetics and numerical computations. By introducing physical models of PCRAM elements, a general macromodel of the phase change random access memory (PCRAM) elements for HSPICE-based computer simulator is proposed. PCRAM array were designed, fabricated, and tested by using a self built tester. Also, near field optical scan microscope incorporated with fs laser was used to fabricate nano scale PCRAM cells

Performance boost for In 0.53 Ga 0.47 As channel N-MOSFET using silicon nitride liner stressor with high tensile stress

We report the first demonstration of a strained In<inf>0.53</inf>Ga<inf>0.47</inf>As n-MOSFET incorporated with a silicon nitride (SiN) liner stressor. High intrinsic tensile stress of 1.5 GPa in a 50 nm thick SiN was used for introducing lateral tensile strain in the In<inf>0.53</inf>Ga<inf>0.47</inf>As channel. SiN liner stressor was shown to provide significant drive current enhancement for the first time. In addition, an advanced gate dielectric technology (with SiH<inf>4</inf> + NH<inf>3</inf> treatment) was used for achieving low interface state densities for HfAlO gate dielectric formed on In<inf>0.53</inf>Ga<inf>0.47</inf>As. Strained In<inf>0.53</inf>Ga<inf>0.47</inf>As n-MOSFETs with good device performance are reported.

Study of geometric effect on phase change random access memory

In this paper, phase change random access memory (PCRAM) devices with two different geometric configurations were studied. The geometry effect on device functionalities in terms of thermal and electrical properties has been analyzed by simulation and experiments. Based on 0.35mum technology, 128 bits PCRAM array integrating with CMOS as the selection device were fabricated. The two types of PCRAM cells were implemented and characterized. The simulation results showed that both the bottom electrode and phase change layer geometry and the size of the interface between the phase change material and the bottom electrode were the determinant factors to the temperature profile and heat distribution. Both simulation and experimental results show that PCRAM device with type II structure required lower current to start phase change from crystalline state to amorphous state. However, it required a larger current to be fully RESET. A model was proposed in this paper to discuss this phenomenon

Thermal Analysis and Structural Design of Phase Change Random Access Memory

A thermal modeling based on Finite Element Method (FEM) was used to simulate Phase Change Random Access Memory (PCRAM) cells. The factors affecting temperature distribution of a PCRAM cell structure such as geometry, device structure and the properties of the individual materials were investigated. The results of the analysis provided the fundamental design of a novel cell structure which has a better performance and reliability.