Honam Kwon

A Gradient Index Liquid Crystal Microlens Array for Light-Field Camera Applications

We have developed a microlens array (MLA) that utilizes liquid crystal (LC) for switching between light field and normal picturing modes in the camera application. The gradient index (GRIN) profile in an LC layer was obtained by applying the electric field distribution between a pair of molded-and-buried concave and planar electrodes. The concave array was formed by the imprinting method with ultraviolet curing resin. An indium tin oxide layer was deposited on the concave array to make the transparent electrode, which was then buried and flattened with the same resin. The transparency and flatness of the electrodes and resin keep the image quality high without applied voltage in the normal mode, and the electrode in the concave shape causes the LC layer to have a GRIN profile that acts as a MLA when voltage is applied in the light-field mode. The fabricated MLA showed suitable mode-switching operations by applying (for light-field mode) or not applying (for normal mode) a voltage of ±4 V.

Compound-Eye Camera Module as Small as 8.5

To promote the widespread use of light-field computational cameras, downsizing of the system is essential. This paper presents an 8.5 mm × 8.5 mm × 6.0 mm tiny compound-eye camera module based on the light field. The camera module is composed of a single-lens unit of a 63° field-of-view (FOV) diagonal, a microlens array (MLA) glued on an 8-Mpix color CMOS sensor (1/3.2” format), and a read-out substrate. The captured raw MLA image is capable of constructing a 26 000-resolution depth image and refocused 2-Mpix 2D RGB images. We also demonstrated that our “image height calibration” and “optical scoring” improved the accuracy of the measured depth and revealed it to be effective for wide-angle FOV optics, such as the lens unit used in our tiny camera module that has the potential for widespread application. Analysis of the depth accuracy proved that the measured depth accuracy with our camera was higher than 90% in the depth range from 5 to 50 cm at the image center.

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We have developed a 22 µm pitch and 320 × 240 pixel uncooled IR (infrared) image sensor. For IR detection, we utilized single crystal silicon series p–n junctions, which were fabricated on a SOI (silicon on insulator) wafer utilizing 8 inch CMOS technology and MEMS processes. The p–n junctions were passivated with buried and laminated oxide layers from wet crystalline etching of the silicon substrate. The oxide layers were also utilized to absorb the IR radiation and to form supporting beams. The partially released pixels were utilized as thermal black pixels (TBs) instead of optical black pixels (OBs) for correlated double sampling. The IR image sensor utilizing TBs obtained a thermal image of the human body stably without the smearing phenomenon.

8.5

We have developed an uncooled infrared radiation focal plane array (IR-FPA) with 22 μm pitch and 320 × 240 pixels utilizing silicon p-n junction diodes, which were fabricated by 0.13 μm CMOS technology and bulk-micromachining. The thermal time response of cells was lowered to be 16msec by reduction of thermal capacity of cells. In addition to increase the sensitivity of cells by extending the length of supporting beams, p-n junction diode was scaled down as small as 20% in area compared to previous one. Micro-holes were formed in the cell to reduce only thermal capacity, which were negligibly small compared to incident IR wavelength. This method needs no additional process step and is considered as suitable for low cost and mass-productive IR-FPA.

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We have developed a 22um pitch and 320 × 240 pixel uncooled infrared radiation focal plane array on the silicon-oninsulator (SOI) substrate by means of 0.35um CMOS technology and bulk-micromachining. For IR detection, we use silicon single-crystal series p-n junctions that can realize high uniformity of sensitivity and low voltage drift. The supporting beam shrinkage enabled the pixel pitch shrinkage from 32um to 22um and 320 × 240 pixel number without deteriorating NETD. We also developed a SOI low-noise CMOS readout circuit that can calibrate chip temperature and introduced a noise canceling digital algorithm to cancel the reset noise generated in the readout circuit. The dominant noise source, SOI MOSFET noise, was decreased by optimizing the gate design. Finally the FPA has realized noise equivalent temperature difference (NETD) of 0.12K and requires no thermo-electric cooler (TEC) and is mounted on a low-cost standard ceramic package.