Hideyuki Funaki

New 1200 V MOSFET structure on SOI with SIPOS shielding layer

In this paper, we have experimentally obtained, for the first time, 1200 V lateral diodes and MOSFETs on SOI. The SOI structure is characterized by a SIPOS layer inserted between the silicon layer and the buried oxide. It was found that the new SOI diode breakdown voltage is determined by the conventional bulk p-n junction theory and not by the resurf (reduced surface field) principle.

Improvement in lateral IGBT design for 500 V 3 A one chip inverter ICs

This paper reports, for the first time, the development of 500 V, 3 A single chip inverter ICs. The chip size of the IC is 7.1/spl times/5.2 mm/sup 2/, which is only 30% larger than that of 500 A, 1 A inverter ICs. The chip size reduction has been realized by 35% improvement in lateral IGBT on-resistance and an optimized layout of LIGBT unit cells and bonding pads.

Multi-channel SOI lateral IGBTs with large SOA

We report, for the first time, the development of 5 ampere multi-channel lateral IGBTs on SOI. The new LIGBTs are characterized by a plural number of parallel stripe poly-silicon gates and resultant plural number of channels, which enhances electron injection and attains a large current capability. The developed LIGBTs conduct current density over 120 A/cm/sup 2/ at the drain voltage of 3 V and simultaneously achieve a fall-time below 300 ns. The LIGBTs have excellent current capability and short circuit withstanding capability of DC 300 V with 500 A/cm/sup 2/ of drain current even at 200/spl deg/C.

A Gradient Index Liquid Crystal Microlens Array for Light-Field Camera Applications

We have developed a microlens array (MLA) that utilizes liquid crystal (LC) for switching between light field and normal picturing modes in the camera application. The gradient index (GRIN) profile in an LC layer was obtained by applying the electric field distribution between a pair of molded-and-buried concave and planar electrodes. The concave array was formed by the imprinting method with ultraviolet curing resin. An indium tin oxide layer was deposited on the concave array to make the transparent electrode, which was then buried and flattened with the same resin. The transparency and flatness of the electrodes and resin keep the image quality high without applied voltage in the normal mode, and the electrode in the concave shape causes the LC layer to have a GRIN profile that acts as a MLA when voltage is applied in the light-field mode. The fabricated MLA showed suitable mode-switching operations by applying (for light-field mode) or not applying (for normal mode) a voltage of ±4 V.

New high voltage SOI device structure eliminating substrate bias effects

The breakdown voltage of a conventional SOI device is limited because it requires a thicker buried oxide as well as a thicker silicon layer. A new SOI device structure and its substrate are proposed to break through these constraints. The proposed new SOI is characterized by a SIPOS (Semi-Insulating POly-crystalline Silicon) layer inserted between the silicon layer and the buried oxide. Since the SIPOS layer effectively shields the influence of the substrate bias, 600 V breakdown voltage SOI diodes and lateral IGBTs were successfully realized using a 0.8 /spl mu/m SIPOS layer and 0.8 /spl mu/m buried oxide.

High voltage BiCDMOS technology on bonded 2 /spl mu/m SOI integrating vertical npn pnp, 60 V-LDMOS and MPU, capable of 200/spl deg/C operation

Trench isolated 60 V BiCDMOS processes on bonded 2 /spl mu/m thick SOI, capable of integrating 60 V low on-resistance lateral DMOS, vertical npn and pnp, and an MPU have been developed. 200/spl deg/C high temperature operation has been demonstrated. The processes are completely compatible with the conventional 0.8 /spl mu/m rule CMOS processes, and are capable of integrating any existing library of MPUs, logic and analog circuits together with 6O V DMOS H bridges.

Tunable light grating integrated with high-voltage driver IC for image projection display

This paper presents a monolithic integration technique of MEMS grating light valves with high-voltage (40 V) driver circuits that target for image projection display devices. Driver circuits were prepared on an 8-mum-thick SOI (Silicon-on- Insulator) wafer by the DMO S (Double-diffused Metal Oxide Semiconductor) processes, after which the MEMS grating were integrated in the identical SOI layer by post-processing using the DRIE (Deep Reactive Ion Etching). In our work, optical light angle is modulated by changing the period of the MEMS grating pixel by means of electrostatic actuation. Optical diffraction angles of 6.6deg (OFF-state) and 3.3 deg (ON-State) were obtained with drive voltage of 0 V and 40 V, respectively.

0.8 µm CMOS Process Compatible 60 V–100 m Ω·mm 2 Power MOSFET on Bonded SOI

In the present paper, we propose high voltage lateral power metal-oxide-semiconductor field effect transistor (MOSFET) on silicon on insulator (SOI), using the pure 0.8 µm complementary metal-oxide-semiconductor (CMOS) processes without diffusion self-alignment. The measured specific on-resistance of the developed lateral power n-channel MOSFET (NMOSFET) was 100 m Ωmm2 and breakdown voltage was 60 V. The fabricated device attains its on-resistance comparable to that of diffusion self-align MOSFET (DMOSFET). It also achieves high side switch operation by a reasonable cost, and can be integrated with Bipolar CMOS (BiCMOS) circuits and micro processing unit (MPU). Compatibility of the developed MOSFET to these low voltage circuits are demonstrated. Furthermore, we show that the MPUs and BiCMOS analog circuit on SOI is suitable for high temperature operation.

A 160 x 120 pixel uncooled TEC-less infrared radiation focal plane array on a standard ceramic package

We have developed a 32 μm pitch and 160 × 120 pixel uncooled infrared radiation focal plane array (IRFPA) on SOI by 0.35 μm CMOS technology and bulk-micromachining. For IR detection, we use silicon single crystal series p-n junctions which can realize high uniformity of temperature coefficient and low voltage drift. We have also developed a low-noise CMOS readout circuit on the same SOI which can calibrate the substrate temperature variation in every frame period, comparing two types of pixels, a bulk-micromachined infrared detection pixel and a non-micromachined reference pixel. Then the FPA requires no thermo-electric cooler (TEC) and is mounted on a low-cost standard ceramic package for the consumer products market.

Lateral SOI diode design optimization for high ruggedness and low temperature dependence of reverse recovery characteristics

This paper compares, for the first time, the maximum controllable current, or SOA of three different diode structures with low efficiency emitters. Low anode emitter efficiency is achieved either by introducing n/sup +/ diffusions in the p-type anode region (n/sup +//p/sup +/ diodes), or by adopting a low surface concentration anode (p/sup -//p/sup +/ diodes), or by shallow p diffusion (shallow p/p/sup +/ diodes). It was found that the n/sup +//p/sup +/ diode was easily destroyed in the reverse recovery transient at a high temperature of 150/spl deg/C because of a parasitic n-p-n transistor action. The best optimization was found in p/sup -//p/sup +/ diodes. Shallow p/p/sup +/ diodes exhibited the same ruggedness, if the dose of the shallow p layer was optimized.