Hong-Hui Chen

Analysis and architecture design of block-coding engine for EBCOT in JPEG 2000

Embedded block coding with optimized truncation (EBCOT) is the most important technology in the latest image-coding standard, JPEG 2000. The hardware design of the block-coding engine in EBCOT is critical because the operations are bit-level processing and occupy more than half of the computation time of the whole compression process. A general purpose processor (GPP) is, therefore, very inefficient to process these operations. We present detailed analysis and dedicated hardware architecture of the block-coding engine to execute the EBCOT algorithm efficiently. The context formation process in EBCOT is analyzed to get an insight into the characteristics of the operation. A column-based architecture and two speed-up methods, sample skipping (SS) and group-of-column skipping (GOCS), for the context generation are then proposed. As for arithmetic encoder design, the pipeline and look-ahead techniques are used to speed up the processing. It is shown that about 60% of the processing time is reduced compared with sample-based straightforward implementation. A test chip is designed and the simulation results show that it can process 4.6 million pixels image within 1 s, corresponding to 2400 /spl times/ 1800 image size, or CIF (352 /spl times/ 288) 4 : 2 : 0 video sequence with 30 frames per second at 50-MHz working frequency.

Lifting based discrete wavelet transform architecture for JPEG2000

A lifting based 1-D discrete wavelet transform (DWT) core is proposed. It is re-configurable for 5/3 and 9/7 filters in JPEG2000. Folded architecture is adopted to reduce the hardware cost and achieve the higher hardware utilization. Multiplication is realized in hardwired multiplier with coefficients represented in canonic signed-digit (CSD) form. It is a compact and efficient DWT core for the hardware implementation of JPEG2000 encoder.

Computation reduction technique for lossy JPEG2000 encoding through EBCOT Tier-2 feedback processing

A novel method to reduce computation of JPEG2000 encoding is proposed. The main concept is that most of the computation in the entropy coder (EBCOT Tier-1) of JPEG2000 is redundancy especially at lower bit-rates, and the proposed method can greatly reduce this redundancy through the feedback of EBCOT Tier-2 processing. By the information generated from Tier-2, the computing time of EBCOT Tier-1 at irreversible wavelet transform mode (9-7 filter) can be reduced to about 40% and 20% at general and high compression rates, respectively. And there is even more reduction at reversible wavelet transform mode (5-3 filter).

Effective hardware-oriented technique for the rate control of JPEG2000 encoding

A great deal of computation for JPEG2000 encoding is a redundancy when the compression rate is high. That is because many coded bit-streams will be truncated after the rate control of JPEG2000. In this paper, an effective scheme for JPEG2000 rate control is proposed. Through this scheme, the computation complexity for JPEG2000 entropy coding, that is, EBCOT Tier-1, can be greatly reduced almost without paying any penalty on the image quality, especially at lower bit-rate. Moreover, the proposed method is considered to be suitable for the hardware implementation since the existing techniques for the rate control of JPEG2000 are all software-oriented. By the proposed rate control method, a dedicated hardware of JPEG2000 with high-speed processing and effective rate control ability can be achieved.

Analysis of EBCOT decoding algorithm and its VLSI implementation for JPEG 2000

Embedded block coding with optimized truncation (EBCOT) is the entropy coding algorithm adopted by the new still image compression standard JPEG 2000. It is composed of a multi-pass fractional bit-plane context scanning along with an arithmetic coding procedure. GPP (general purpose processor) or DSP fails to accelerate this kind of bit-level operation, which is proven to occupy most of the computational time of the JPEG 2000 system. In this paper, two new accelerating schemes are proposed and applied to our prototyping design which turns out to be powerful enough to fulfill the demand of computational requirement of the most advanced digital still camera.

Seizure prediction based on classification of EEG synchronization patterns with on-line retraining and post-processing scheme

Epilepsy is one of the most common brain disorders in the world. The spontaneous seizure onset influences the daily life of epilepsy patients. The studies on feature extraction and feature classification from Electroencephalography(EEG) signal in seizure prediction methods have shown great improvement these years. However, the variation issue of EEG signal (being awake, being asleep, severity of epilepsy, etc.) poses a fundamental difficulty in seizure prediction problem. The traditional off-line training method trains the model using a fixed training set, and expects the performance of the model to remain stable even after a long period of time, and thus suffers from variation issue. In this paper, we propose an on-line retraining method to leverage the recent input data by gradually enlarging the training set and retraining the model. Also, a simple post-processing scheme is incorporated to reduce false alarms. We develop our method based on the state of the art machine learning based classification of bivariate patterns method. The performance of the method is evaluated on Electrocorticogram(ECoG) recording from Freiburg database as well as long-term scalp EEG recording from CHB-MIT EEG Database and National Taiwan University Hospital. The proposed method achieves 74.2% sensitivity on ECoG database and 52.2% sensitivity on scalp EEG database, while improving the sensitivity of off-line training method by 29.0% and 17.4% in ECoG database and EEG database respectively. The experimental result suggests that on-line retraining can greatly improve the reliability and is promising for future seizure prediction method development.

Analysis and architecture design of lifting based DWT and EBCOT for JPEG 2000

Analysis and architecture design for two major parts of JPEG 2000, discrete wavelet transform (DWT) and embedded block coding with optimized truncation (EBCOT), are presented in this paper. For DWT, a configurable lifting based 1-D DWT core for both 5-3 and 9-7 filters is proposed. Folded architecture is adopted in DWT to reduce the hardware cost and to achieve the higher hardware utilization. For EBCOT, column-based coding architecture of Tier-1 coding with three speedup methods is proposed. Computation time of context formation in EBCOT can be reduced up to 70%.

23.2 A 1920×1080 30fps 611 mW five-view depth-estimation processor for light-field applications

Depth information has become essential in emerging computer vision applications. Although active sensing methods can provide an accurate indoor depth map, they have limited resolution and consume significant power, such as the 2.1W time-of-flight sensor in [1]. In contrast, depth estimation for stereo RGB images can provide high-resolution depth maps, even in outdoor or low-power scenarios. And, the depth accuracy can be increased by using multi-view light-field images. This paper presents an integrated circuit which estimates full HD (1920×1080) depth maps at 30fps and provides a tradeoff between depth accuracy and power consumption based on two-/three-/five-view stereo images. It addresses design challenges with three primary contributions: 1) a stripe buffering scheme which is designed to reduce the DRAM bandwidth induced by multi-view image access; 2) a four-bank interleaving architecture, which boosts computation performance by parallelizing belief-propagation (BP) operations; and, 3) an adaptive view selection unit, which realizes the accuracy-power tradeoff.

Robust heart rate measurement with phonocardiogram by on-line template extraction and matching

As health care becomes popular, daily monitoring of health-status related parameters, including the heart rate (HR), is getting more and more valued. An easy, comfortable and robust solution is therefore an important issue. Phonocardiogram (PCG) is a physiological signal reflecting the cardiovascular status. It could be recorded by microphone-equipped on-hand devices, like the smartphone, even without direct skin contact. However, high inter- and intra-variance of PCG make its processing challenging. For PCG-based HR measurement, a robust method is still strongly required. In this paper, we propose a HR measurement algorithm on the processing of PCG that uses on-line template extraction and matching. Through several experiments where traditional methods cannot effectively handle, the robustness of our method is verified by its accurate HR measurement results.

Analysis and design of on-sensor ECG processors for realtime detection of VF, VT, and PVC

Cardiovascular disease remains the main cause of death, and great efforts are spent on the design of ECG body sensors these years. Essential components such as analog frontend and wireless transceivers have been integrated on a compact IC with micro-Watt power consumption. To provide timely warning against the fatal vascular signs, based on the Chaotic Phase Space Differential (CPSD) algorithm, on-sensor processors are implemented to detect the abnormal ECG for VF, VT and PVC. The on-sensor processing reduces 98.0% power of wireless data transmission for raw ECG signals. The application specific processor is designed to accelerate CPSD algorithm with 1.7μW power while the OpenRISC is integrated to provide the system flexibility. The architecture is realized on the FPGA platform to physically demonstrate the detection of the abnormal ECG signals in a real time.