Chung-Jr Lian

Analysis and architecture design of block-coding engine for EBCOT in JPEG 2000

Embedded block coding with optimized truncation (EBCOT) is the most important technology in the latest image-coding standard, JPEG 2000. The hardware design of the block-coding engine in EBCOT is critical because the operations are bit-level processing and occupy more than half of the computation time of the whole compression process. A general purpose processor (GPP) is, therefore, very inefficient to process these operations. We present detailed analysis and dedicated hardware architecture of the block-coding engine to execute the EBCOT algorithm efficiently. The context formation process in EBCOT is analyzed to get an insight into the characteristics of the operation. A column-based architecture and two speed-up methods, sample skipping (SS) and group-of-column skipping (GOCS), for the context generation are then proposed. As for arithmetic encoder design, the pipeline and look-ahead techniques are used to speed up the processing. It is shown that about 60% of the processing time is reduced compared with sample-based straightforward implementation. A test chip is designed and the simulation results show that it can process 4.6 million pixels image within 1 s, corresponding to 2400 /spl times/ 1800 image size, or CIF (352 /spl times/ 288) 4 : 2 : 0 video sequence with 30 frames per second at 50-MHz working frequency.

Lifting based discrete wavelet transform architecture for JPEG2000

A lifting based 1-D discrete wavelet transform (DWT) core is proposed. It is re-configurable for 5/3 and 9/7 filters in JPEG2000. Folded architecture is adopted to reduce the hardware cost and achieve the higher hardware utilization. Multiplication is realized in hardwired multiplier with coefficients represented in canonic signed-digit (CSD) form. It is a compact and efficient DWT core for the hardware implementation of JPEG2000 encoder.

Hardware architecture design of an H.264/AVC video codec

H.264/AVC is the latest video coding standard. It significantly outperforms the previous video coding standards, but the extraordinary huge computation complexity and memory access requirement make the hardwired codec solution a tough job. This paper describes the design methodology for H.264/AVC video codec. The system architecture and scheduling are addressed. The design consideration and optimization for its significant modules including bandwidth optimized motion compensation engine, reconfigurable intra predictor generator, low bandwidth parallel integer motion estimation are mentioned. Due to the complex, sequential, and highly data-depended characteristics of all essential algorithms in H.264/AVC, not only the pipeline structure but also efficient memory hierarchy is required. The design case with a hybrid task pipelining scheme, a balanced schedule with block-level, MB-level, and frame-level pipelining, are presented. By combining with many bandwidth reduction techniques and data reused schemes, very efficient architecture and implementation for plate-form based system is proved by the prototype chips

Power-aware multimedia: concepts and design perspectives

© C O M S T O C K Feature

High speed memory efficient EBCOT architecture for JPEG2000

This paper presents a high speed, memory efficient architecture of embedded block coding with optimized truncation (EBCOT) tier-1 in JPEG2000. By parallel coding all the bitplanes, the state variable memory can be eliminated. The proposed architecture can process 50 M coefficients per second at 100 MHz, which can realtime encode 720p resolution of HDTV picture format at 30 fps.

81MS/s JPEG2000 single-chip encoder with rate-distortion optimization

An 81MS/s JPEG 2000 single-chip encoder is implemented on a 5.5mm/sup 2/ die using 0.25/spl mu/m CMOS technology. This IC can encode HDTV 720p resolution at 30 frames/s in real time. The rate-distortion optimized chip encodes tile size of 128/spl times/128, code block size of 64/spl times/64, and image size up to 32K/spl times/32K.

Parallel embedded block coding architecture for JPEG 2000

This paper presents a parallel architecture for the Embedded Block Coding (EBC) in JPEG 2000. The architecture is based on the proposed word-level EBC algorithm. By processing all the bit planes in parallel, the state variable memories for the context formation (CF) can be completely eliminated. The length of the FIFO (first-in first-out) between the CF and the arithmetic encoder (AE) is optimized by a reconfigurable FIFO architecture. To reduce the hardware cost of the parallel architecture, we proposed a folded AE architecture. The parallel EBC architecture can losslessly process 54 MSamples/s at 81 MHz, which can support HDTV 720p resolution at 30 frames/s.

Computation reduction technique for lossy JPEG2000 encoding through EBCOT Tier-2 feedback processing

A novel method to reduce computation of JPEG2000 encoding is proposed. The main concept is that most of the computation in the entropy coder (EBCOT Tier-1) of JPEG2000 is redundancy especially at lower bit-rates, and the proposed method can greatly reduce this redundancy through the feedback of EBCOT Tier-2 processing. By the information generated from Tier-2, the computing time of EBCOT Tier-1 at irreversible wavelet transform mode (9-7 filter) can be reduced to about 40% and 20% at general and high compression rates, respectively. And there is even more reduction at reversible wavelet transform mode (5-3 filter).

Effective hardware-oriented technique for the rate control of JPEG2000 encoding

A great deal of computation for JPEG2000 encoding is a redundancy when the compression rate is high. That is because many coded bit-streams will be truncated after the rate control of JPEG2000. In this paper, an effective scheme for JPEG2000 rate control is proposed. Through this scheme, the computation complexity for JPEG2000 entropy coding, that is, EBCOT Tier-1, can be greatly reduced almost without paying any penalty on the image quality, especially at lower bit-rate. Moreover, the proposed method is considered to be suitable for the hardware implementation since the existing techniques for the rate control of JPEG2000 are all software-oriented. By the proposed rate control method, a dedicated hardware of JPEG2000 with high-speed processing and effective rate control ability can be achieved.

Analysis of EBCOT decoding algorithm and its VLSI implementation for JPEG 2000

Embedded block coding with optimized truncation (EBCOT) is the entropy coding algorithm adopted by the new still image compression standard JPEG 2000. It is composed of a multi-pass fractional bit-plane context scanning along with an arithmetic coding procedure. GPP (general purpose processor) or DSP fails to accelerate this kind of bit-level operation, which is proven to occupy most of the computational time of the JPEG 2000 system. In this paper, two new accelerating schemes are proposed and applied to our prototyping design which turns out to be powerful enough to fulfill the demand of computational requirement of the most advanced digital still camera.