Hong Zhiliang

High efficiency, inductorless step-down DC/DC converter

A high efficiency, inductorless step-down DC/DC converter is proposed. High efficiency is achieved through the combination of the fractional conversion ratio charge pump and load current sensing circuit. The circuits have been designed in the TSMC 0.25mum 2.5V/5V mixed signal CMOS process. The DC/DC converter has an output voltage of 1.8V (load current les 200mA) with the accuracy of plusmn 1% and the ripple voltage less than plusmn10mV for the input battery voltage from 2.8V to 5V. The peak and average efficiency is over 85% and 65%, respectively

A low power 12-bit 200-kS/s SAR ADC with a differential time domain comparator

A low power 12-bit 200-kS/s SARADC is proposed. This features a differential time domain comparator whose offset is cancelled by using a charge pump and a phase frequency detector instead of the preamplifiers usually needed in a high resolution comparator. The proposed ADC is manufactured in 0.18-μm CMOS technology and the measured SNR and SNDR are 62.5 dB and 59.3 dB, respectively, with a power consumption of 72 μW at a 200-kS/s sampling rate. The device operates with a 1.8-V power supply and achieves a FOM of 477 fJ/conversion-step.

A single-inductor dual-output switching converter with average current mode control

An integrated single-inductor dual-output (SIDO) switching DC–DC converter is presented. The outputs are specified with 1.2 V/400 mA and 1.8 V/200 mA. A decoupling small signal model is proposed to analyze the multi-loop system and to design the on-chip compensators. An average current control mode is introduced with lossless, continuous current detection. The converter has been fabricated in a 0.25 μm 2P4M CMOS process. The power efficiency is 86% at a total output power of 840 mW while the output ripples are about 40 mV at an oscillator frequency of 600 kHz.

A fully integrated BPSK amplitude and spectrum tunable transmitter for IR-UWB system

A 3–5 GHz low power BPSK modulated impulse radio UWB transmitter is implemented in 0.13 μm CMOS technology. In this design the amplitude and spectrum of the output impulse are both tunable to solve the special problem in IR-UWB, where it is difficult to control the spectrum. Measurement results indicate that, by changing the control bits in the gain control circuit and differential circuit, the 3-step peak-to-peak voltage amplitudes are 240, 170 and 115 mV and the center frequency of the impulse can be tuned from 3.2 to 4.1 GHz. A power controlled output buffer is designed to drive the antenna. The total power consumption is only 4.44 mW when transmitting a baseband signal of 100 MHz. The chip area is 1.2 × 1.4 mm2.

A low-power portable ECG sensor interface with dry electrodes

This paper describes a low-power portable sensor interface dedicated to sensing and processing electrocardiogram (ECG) signals. Dry electrodes were employed in this ECG sensor, which eliminates the need of conductive gel and avoids complicated and mandatory skin preparation before electrode attachment. This ECG sensor system consists of two ICs, an analog front-end (AFE) and a successive approximation register analog-to-digital converter (SAR ADC) containing a relaxation oscillator. This proposed design was fabricated in a 0.18 μm 1P6M standard CMOS process. The AFE for extracting the biopotential signals is essential in this ECG sensor. In measurements, the AFE obtains a mid-band gain of 45 dB, a bandwidth from 0.6 to 160 Hz, and a total input referred noise of 2.8 μV rms while consuming 1 μW from the 1.8 V supply. The noise efficiency factor (NEF) of our design is 3.4. After conditioning, the amplified ECG signal is digitized by a 12-bit SAR ADC with 61.8 dB SNDR and 220 fJ/conversion-step. Finally, a complete ECG sensor interface with three dry copper electrodes is demonstrated in real-word setting, showing successful recordings of a capture ECG waveform.

A multi-path gated ring oscillator based time-to-digital converter in 65 nm CMOS technology

A gated ring oscillator (GRO) based time-to-digital converter (TDC) is presented. To enhance the resolution of the TDC, a multi-path structure for the GRO is used to achieve a higher oscillation frequency and an input stage is also presented to equivalently amplify the input time difference with a gain of 2. The GRO based TDC circuit is fabricated in TSMC 65 nm CMOS technology and the core area is about 0.02 mm2. According to the measurement results, the effective resolution of this circuit is better than 4.22 ps under a 50 MHz clock frequency. With a 1 ns input range, the maximum clock frequency of this circuit is larger than 200 MHz. Under a 1 V power supply, with a 200–800 ps input time difference, the measured power consumption is 1.24 to 1.72 mW at 50 MHz clock frequency and 1.73 to 2.20 mW at 200 MHz clock frequency.

A 455 nW 220 fJ/conversion-step 12 bits 2 kS/s SAR ADC for portable biopotential acquisition systems

An ultra-low power 12 bits 2 kS/s successive approximation register analog-to-digital converter (ADC) is presented. For power optimization, the voltage supply of the digital part is lowered, and the offset voltage of the latch is self-calibrated. Targeted for better linearity and lower noise, an improved digital-to-analog converter capacitor array layout strategy is presented, and a low kick-back noise latch is proposed. The chip was fabricated by using 0.18 μm 1P6M CMOS technology. The ADC achieves 61.8 dB SNDR and dissipates 455 nW only, resulting in a figure of merit of 220 fJ/conversion-step. The ADC core occupies an active area of only 674 × 639 μm2.

A 434/868 MHz CMOS low-IF receiver with I/Q imbalance calibration for SRDs application

A receiver for SRDs implemented by the 0.35 μm CMOS process is presented. The receiver, together with the ADC, power amplifier (PA), frequency synthesizer and digital baseband has been integrated into a single chip solution. Low cost and low power requirements are met by optimizing the receiver architecture and circuit topology. A simple mixed-signal mode I/Q imbalance calibration circuit is proposed to enhance the IRR (image rejection ratio) so as to raise the BER. From a single 3 V power supply, the receiver consumes 5.9 mA. The measurement result shows that the receiver achieves reference sensitivity of s−60 dBm and a control gain of 60 dB. The S11 reaches −20 dB at 433 MHz and −10 dB at 868 MHz without off-chip impedance match network. The die area is only 2 mm2 including the bias circuit.

A 10 MHz ripple-based on-time controlled buck converter with dual ripple compensation

A 10 MHz ripple-based on-time controlled buck converter is presented. A novel low-cost dual ripple compensation, which consists of coupling capacitor compensation and passive equivalent series resistance compensation, is proposed to achieve a fast load transient response and robust stability simultaneously. Implemented in a 2P4M 0.35 μm CMOS process, the converter achieves fix-frequency output with a ripple of below 10 mV and an overshoot of 10 mV at 400 mA step load transient response. With width optimization of the power transistors in an ultra-heavy load and PFM control in a light load, the efficiency stays at over 83% for a load range from 20 mA to 1.5 A and the peak efficiency reaches 90.16%.

A Capacitive Step-Down Converter Using a Linear Mode Pre-Regulator for Improved Load Regulation

A capacitive step-down converter in 0.25 mum CMOS using a linear mode pre-regulator is presented. The linear pre-regulator operates both in pulse frequency mode under low load conditions and in current mode under high output load. In pulse frequency mode the pre-regulator limits the charge current of the capacitor network improving the electromagnetic compatibility. Under high load conditions the converter operates in a current mode which means that the switched capacitors are clocked with a fixed duty cycle ratio and the regulation of the output voltage is performed by the pre-regulator