Yi Ting

A low power 12-bit 200-kS/s SAR ADC with a differential time domain comparator

A low power 12-bit 200-kS/s SARADC is proposed. This features a differential time domain comparator whose offset is cancelled by using a charge pump and a phase frequency detector instead of the preamplifiers usually needed in a high resolution comparator. The proposed ADC is manufactured in 0.18-μm CMOS technology and the measured SNR and SNDR are 62.5 dB and 59.3 dB, respectively, with a power consumption of 72 μW at a 200-kS/s sampling rate. The device operates with a 1.8-V power supply and achieves a FOM of 477 fJ/conversion-step.

A low power low noise analog front end for portable healthcare system

The presented analog front end (AFE) used to process human bio-signals consists of chopping instrument amplifier (IA), chopping spikes filter and programmable gain and bandwidth amplifier. The capacitor-coupling input of AFE can reject the DC electrode offset. The power consumption of current-feedback based IA is reduced by adopting capacitor divider in the input and feedback network. Besides, IAs input thermal noise is decreased by utilizing complementary CMOS input pairs which can offer higher transconductance. Fabricated in Global Foundry 0.35 μm CMOS technology, the chip consumes 3.96 μA from 3.3 V supply. The measured input noise is 0.85 μVrms (0.5–100 Hz) and the achieved noise efficient factor is 6.48.

A current-steering self-calibration 14-bit 100-MSPs DAC

This paper presents the design and implementation of a 14-bit, 100 MS/s CMOS digital-to-analog converter (DAC). Analog background self-calibration based on the concept of analog current trimming is introduced. A constant clock load switch driver, a calibration period randomization circuit and a return-to-zero output stage have been adopted to improve the dynamic performance. The chip has been manufactured in a SMIC 0.13-μm process and occupies 1.33 × 0.97 mm2 of the core area. The current consumption is 50 mA under 1.2/3.3 V dual power supplies for digital and analog, respectively. The measured differential and integral nonlinearity is 3.1 LSB and 4.3 LSB, respectively. The SFDR is 72.8 dB at a 1 MHz signal and a 100 MHz sampling frequency.

A 18-mW, 20-MHz bandwidth, 12-bit continuous-time Σ Δ modulator using a power-efficient multi-stage amplifier

A fourth-order continuous-time sigma delta modulator with 20-MHz bandwidth, implemented in 130-nm CMOS technology is presented. The modulator is comprised of an active-RC operational-amplifier based loop filter, a 4-bit internal quantizer and three current steering feedback DACs. A three-stage amplifier with low power is designed to satisfy the requirement of high dc gain and high gain-bandwidth product of the loop filter. Non-return-to-zero DAC pulse shaping is utilized to reduce clock jitter sensitivity. A special layout technique guarantees that the main feedback DAC reaches 12-bit match accuracy, avoiding the use of a dynamic element matching algorithm to induce excess loop delay. The experimental results demonstrate a 64.6-dB peak signal-to-noise ratio, and 66-dB dynamic range over a 20-MHz signal bandwidth when clocked at 480 MHz with 18-mW power consumption from a 1.2-V supply.

A low-power triple-mode sigma—delta DAC for reconfigurable (WCDMA/TD-SCDMA/GSM) transmitters

A sigma—delta (ΣΔ) DAC with channel filtering for multi-standard wireless transmitters used in the software-defined-radio (SDR) system is presented. The conversion frequency, transfer function of the digital filter and the ΣΔ modulator, word-length of the IDAC and cut-off frequency of the analog reconstruction filter can be digitally programmed to satisfy specifications of WCDMA, TD-SCDMA and GSM standards. The ΣΔ DAC fabricated in SMIC 0.13-μm CMOS process occupies a die area of 0.72 mm2, while consuming 5.52/4.82/3.04 mW in WCDMA/TD-SCDMA/GSM mode from a single 1.2-V supply voltage. The measured SFDR is 62.8/60.1/75.5 dB for WCDMA/TD-SCDMA/GSM mode, respectively.

Optimal design of multiplierless FIR filter

A new structure proposed in this paper, which synthesizes a half-band filter by multiple use of the subfilters saves the hardware cost greatly. Then the coefficient optimization based on simulated annealing algorithms is developed and it obtains better the frequency response performance of the filter than the coefficient optimization based on greedy algorithms, such as local search.A new structure proposed in this paper, which synthesizes a half-band filter by multiple use of the subfilters saves the hardware cost greatly. Then the coefficient optimization based on simulated annealing algorithms is developed and it obtains better the frequency response performance of the filter than the coefficient optimization based on greedy algorithms, such as local search.