Honghui Deng

Design of a high-performance brokaw band-gap reference

A high-performance CMOS band-gap reference (BGR) is designed in this paper. The proposed circuit employs the current-mode architecture optimized for low supply voltage applications. The key portion of the circuit employs the Brokaw BGR architecture, in which a three-stage operational amplifier is adopted to get high PSRR and only first-order temperature compensation technology is employed to get a low temperature coefficient. The circuit is on the Chartered 0.18 μ m CMOS process under the operating voltage of 1.8V and its simulation results are presented. The simulation results show that the temperature coefficient is 9 ppm/°K over the −40°C to 125°C temperature range and the fluctuation of reference voltage is within 0.067m V when the power voltage changes from 1.44V to 2.16V. In addition, the PSRR is 108.5dB at 10 kHz, and the power consumption is only 0.355mW1

Design of a high precision band-gap reference with piecewise-linear compensation

A high precision band-gap reference (BGR) with piecewise-linear compensation is designed in this paper. A low voltage Brokaw BGR architecture is employed to provide low output voltage. A high gain, low power supply rejection ratio (PSRR) operational amplifier is designed to improve the PSRR of the band-gap reference. In order to achieve temperature stability significantly lower than the traditional band-gap reference, a circuit which produces a current with positive temperature coefficient (TC) at high temperatures and 0 current at lower temperatures is designed. The whole BGR circuits are simulated by Spectre based on chartered 0.18μm 1P5M 1.8V CMOS technology. Its clear from simulation result that the TC of the output reference voltage approaches 2.61ppm/K over the military temperature range, the PSRR reaches 107.2dB at low frequency (f=0.1HZ), the whole BGR dissipates 0.4mW. In addition, the output reference voltage changes only 8.6μV when the power supply changes from 1.5V to 2.1V, that is to say, the power regulation ratio is 0.014mV/V.

A high-performance bootstrap switch for low voltage switched-capacitor circuits

A high-performance bootstrap switch for low-voltage switched-capacitor (SC) circuits is presented. The switch enables the precise sampling of input signals on a low voltage supply with high speed, low nonlinear distortion. Experimental results in TSMC 130nm CMOS process show that a peak signal-to-noise-and-distortion ratio (SNDR) of 102.8 dB, spurious-free dynamic range (SFDR) of 104.6 dB and total harmonic distortion (THD) of 105 dB can be acquired at 125 MSample/s.

Design of low-jitter clock duty cycle stabilizer in high-performance pipelined ADC

This paper introduces a design of clock duty cycle stabilizer (DCS) for high-speed pipelined ADC, and analyses the internal parameters on the impact of the circuit performance. Circuit module includes programmable clock input buffer, clock synthesizer, duty cycle detection circuit and nonoverlapping clock generation circuit. The circuit and layout are achieved by 0.18 μm CMOS 1P5M Mixed Signal process. The Cadence Spectre post-simulation results show: The circuit can work for a wide frequency range from 20MHz to 250MHz; duty cycle accuracy of (50±0.25) %, in the 250MHz input frequency, the RMS jitter is 53 fs. The measured performance shows it can work with high speed, high precision and low jitter characteristics, being not strictly requirement on the input clock signal, nonoverlapping time controllable.

A 8-bit 10MS/s asynchronous SAR ADC with resistor-capacitor array DAC

This paper presents a 65nm 8-bit 10MS/s asynchronous successive approximation register analog to digital converter (SAR ADC). This SAR ADC adopts resistor-capacitor array digital to analog converter (DAC) that has more advantages than only resistors or capacitors. This kind of DAC reduces the capacitance area, while ensuring that the DAC processes good integral nonlinearity and differential nonlinearity. In addition, the design uses asynchronous sequential logic control to ensure that SAR ADC regular operates by the feedback signals from comparator when comparison is completed, avoiding the application of high-speed clock. In terms of both power and speed, it can be very good improvement. This design uses the SMIC 65nm CMOS process, simulation results indicate that at 10MS/s sampling frequency, which is Nyquist sampling, with analog power of 2.5V and digital power of 1.2V, the maximum integral nonlinearity error is 0.8LSB, the maximum differential nonlinearity error is 0.5LSB and ENOB is up to 7.8bit.

A high precision CMOS band-gap reference with exponential curvature-compensation

An exponential curvature compensation technique for the high precision band-gap reference (BGR) is presented in this paper, in order to reduce the temperature coefficient (TC) of the traditional band-gap reference, the circuit exploits the temperature characteristics of the current gain ß of BJTs, and generates the current which has non-linear relationship with the temperature to compensate for the higher-order term of the BGR. The compensation circuit adopts a different bipolar current mirror, which can reduce the current error greatly, and the use of native nmos instead of bipolar makes the BGR worked normally under a relatively low supply voltage and the MOST mirrored current can be more accurate. The whole BGR circuits are simulated by Spectre based on chartered 0.18μm 1P5M 1.8V CMOS technology. The simulation shows the temperature coefficient of the output voltage reaches 1.85ppm/K over the military temperature range of -40°C to +125°C, the Power Supply Rejection Ratio (PSRR) of the reference voltage achieves 58.8dB at low frequency(f=0.1Hz), the settling time is 370 ns and the band-gap reference can work normally in all process corners.

The first stage design of a SHA-less 12-bit 200-Ms/s pipeline ADC in 130-nm CMOS

A first stage of a SHA-less 12-bit 200 MSps pipeline analog-to-digital converter (ADC) is designed in this paper. A high speed and high precision comparator is designed in order to reduce the transmission delay of the comparator. RC network of the multiplying digital-to-analog converter (MDAC) and Sub-ADC should be strict matched in order to reduce the sampling errors between the two path. The prototype circuit, implemented in SMIC 130nm 1P5M CMOS process under 1.2V power supply with a 94MHz input signal and 200MHz sampling clock, demonstrates a SNDR of 82.7dB, a SNR of 72.6dB, and a ENOB of 11.83 bit.

A differential reference voltage source and its output buffer used in high-speed high-precision pipelined ADC

An analysis of performance degradation due to limited precision of reference voltage for pipelined ADC (Analog to Digital Converter) is presented in this paper. For the MDAC (multiplying D/A converter) and subADC in pipelined ADC have very different requirements for the precision of reference voltage, an improved differential reference voltage source and its buffer circuit is proposed. The reference voltage for MDAC and subADC are provided and designed the output buffer separately, so that to reduce the crosstalk between MDAC and subADC. Also, the driving ability of the proposed circuit is controllable with the help of programmable bias circuit which regulates the circuits entire power consumption. Spectre post-layout simulation results show that the reference source has the minimum power of 15mW, and the entire set-up time is 5.842ns; has the maximum power of 58mW, and the entire set-up time is 1.036ns. The reference source can meet the requirement of 14-bit 80MSPS to 450MSPS pipelined ADC.

Design of sample and hold merged with 2.5 bit multiplying digital-to-analog converter

A design of a SHA merged with MDAC(SMDAC) which can be used in a 14 bit 80Msps pipelined analog-to-digital converter (ADC) is presented in this paper. A two-stage transconductance-controlled op-amp is used in the SMDAC to ensure the requirement of the resolution, speed and stability of the circuit when its feedback factor alternate between 1/2 and 1/4. Simulation by cadence based on Chartered 0.18μ 1P5M CMOS process under 1.8V supply voltage shows 116dB loop gain, 1.05GHz unity gain bandwidth and 61° phase margin in two different feedback factors of the op-amp. The output signal of the S/H phase and MDAC phase can be settled to 14bit and 12bit accuracy in 5ns, respectively.

Opamp-sharing MDAC design for pipelined successive-stage of a 1.8V 80MS/s 14-bit pipelined ADC

A design of opamp-sharing multiplying digital-to-analog converter (MDAC) used in the successive stages of an 80MS/s 14-bit pipelined analog-to-digital converter (ADC) with 1.8V supply voltage is presented in this paper. Opamp-sharing structure of the paper is proposed to achieve low-power operation, and SC-CMFB (switch capacitor-common mode feedback) circuit further reduces power consumption. The gain-boost structure of the amplifier is used to meet the precision requirement of the MDAC. The memory effect is completely eliminated with clock-resetting phase. The circuit design is implemented in the Chartered 0.18um CMOS process and the simulation results show that the designed MDAC could meet performance requirements of the pipelined ADC, consuming 10.5mW power.