Yongsheng Yin

Phase noise analysis and design of CMOS differential ring VCO

A complete six-order CMOS differential ring voltage-controlled oscillator (VCO) is designed with a 0.35/m CMOS process in this paper. The circuit has been successfully applied in a CPPLL of a high-speed high-resolution DAC, and has been successfully taped out and passed the test. The relative factors that influence the VCO phase noise are analyzed comprehensively to instruct the circuit design. The designed differential ring oscillator includes the VCO unit circuit, the bias circuit for the tail current source, the start-up circuit, and the wave shaping circuit. The oscillation frequency of the designed VCO ranges from 96MHz to 400MHz. An improved VCO unit circuit was adopted to reduce the process influence and the coupling between the output and the ground, as well as to lower the phase noise by connecting a sub-pF magnitude capacitance to the output terminal. Moreover, the start-up circuit is designed to ensure that the VCO could start to oscillate quickly, and the optimal layout is designed to lower the influence of the noise. The circuit is simulated using 0.35μm CMOS process, the simulation results illustrate that the KVCO exhibits an ideal linearity with a value of 467MHz/V and the phase noise has been lowered effectively with a value of −135dBc/Hz@1MHz in the typical operation condition. The test results show that the designed VCO could work properly and the CPPLL could be locked quickly. The designed VCO circuit could be applied in the electronic measurement equipments, providing a controllable and stable frequency signal for the system.

Design of a high-performance brokaw band-gap reference

A high-performance CMOS band-gap reference (BGR) is designed in this paper. The proposed circuit employs the current-mode architecture optimized for low supply voltage applications. The key portion of the circuit employs the Brokaw BGR architecture, in which a three-stage operational amplifier is adopted to get high PSRR and only first-order temperature compensation technology is employed to get a low temperature coefficient. The circuit is on the Chartered 0.18 μ m CMOS process under the operating voltage of 1.8V and its simulation results are presented. The simulation results show that the temperature coefficient is 9 ppm/°K over the −40°C to 125°C temperature range and the fluctuation of reference voltage is within 0.067m V when the power voltage changes from 1.44V to 2.16V. In addition, the PSRR is 108.5dB at 10 kHz, and the power consumption is only 0.355mW1

Current switch driver and current source designs for high-speed current-steering DAC

Based on analyzing of the influence of the current switch driver on dynamic performance of the high-speed current-steering DAC, several key points of designing the current switch driver are proposed. The low cross-point method, synchronous flip-latch and limited swing of switch driver are introduced, and a current switch driver circuit is proposed. In order to further improve the dynamic performance of the DAC, this paper presents a high output impedance current source circuit. A gain stage is utilized in the biasing circuit of the current source, and the output impedance of the proposed current reaches 108 Omega, which is important to fulfill the performance requirements of the DAC. A 14-bit high-speed DAC is designed using the currentswitch driver and current source under a 0.35 mum CMOS process. When the frequency of the full-range input signal is 24.6 MHZ and the sample frequency is 140 MSPS, the SFDR of the DAC achieves 78.2 dB.And the settling time is about 10 ns.

Design of a high precision band-gap reference with piecewise-linear compensation

A high precision band-gap reference (BGR) with piecewise-linear compensation is designed in this paper. A low voltage Brokaw BGR architecture is employed to provide low output voltage. A high gain, low power supply rejection ratio (PSRR) operational amplifier is designed to improve the PSRR of the band-gap reference. In order to achieve temperature stability significantly lower than the traditional band-gap reference, a circuit which produces a current with positive temperature coefficient (TC) at high temperatures and 0 current at lower temperatures is designed. The whole BGR circuits are simulated by Spectre based on chartered 0.18μm 1P5M 1.8V CMOS technology. Its clear from simulation result that the TC of the output reference voltage approaches 2.61ppm/K over the military temperature range, the PSRR reaches 107.2dB at low frequency (f=0.1HZ), the whole BGR dissipates 0.4mW. In addition, the output reference voltage changes only 8.6μV when the power supply changes from 1.5V to 2.1V, that is to say, the power regulation ratio is 0.014mV/V.

Dual-ADC based digital calibration of timing skew for a time-interleaved ADC

The performance of time-interleaved analog-to-digital converters (TIADCs) is seriously restricted by the mismatch of the timing skew between ADC channels. The concept of dual-ADC based calibration is that setting two ADC to sample the same input signal synchronously, and the differences of the two outputs are used in calibration algorithm to estimate and compensate the errors in each ADC. Based on this method, we propose a novel 7-channel TIADC with digital background calibration, which focuses on calibrating the timing skew of each ADC channel. The calibration algorithm is based on the least-mean-square iteration. Simulation of the designed 14-bit 7-channel TIADC with MATLAB shows that, with ± 0.02Ts timing skew, and normalized input frequency fin/fs=0.05, signal to noise and distortion ratio and spurious free dynamic range of the output signal of the TIADC after calibration reach 85.9dBc and 103dBc, and improve 28dBc and 43dBc, respectively, compared to the uncalibrated output signal.

All-digital background calibration technique for timing mismatch of time-interleaved ADCs

An all-digital background calibration technique for timing mismatch of Time-Interleaved ADCs (TIADCs) is presented. The timing mismatch is estimated by performing the correlation calculation of the outputs of sub-channels in the background, and corrected by an improved fractional delay filter based on Farrow structure. The estimation and correction scheme consists of a feedback loop, which can track and correct the timing mismatch in real time. The proposed technique requires only one filter compared with the bank of adaptive filters which requires (M-1) filters in a M-channel TIADC. In case of a 8 bits four-channel TIADC system, the validity and effectiveness of the calibration algorithm are proved by simulation in MATLAB. The proposed architecture is further implemented and validated on the Altera FPGA board. The synthesized design consumes a few percentages of the hardware resources of the FPGA chip, and the synthesized results show that the calibration technique is effective to mitigate the effect of timing mismatch and enhances the dynamic performance of TIADC system. The all-digital background calibration technique for timing mismatch is estimated by performing the correlation calculation of the outputs of sub-channels in the background, and corrected by an improved fractional delay filter based on Farrow structure.The estimation and correction scheme consists of a feedback loop, which can track and correct the timing mismatch in real time.The proposed timing mismatch estimation and correction scheme can effectively enhance the signal to noise ration of TIADC system with the merits of less hardware resources.

A high-performance bootstrap switch for low voltage switched-capacitor circuits

A high-performance bootstrap switch for low-voltage switched-capacitor (SC) circuits is presented. The switch enables the precise sampling of input signals on a low voltage supply with high speed, low nonlinear distortion. Experimental results in TSMC 130nm CMOS process show that a peak signal-to-noise-and-distortion ratio (SNDR) of 102.8 dB, spurious-free dynamic range (SFDR) of 104.6 dB and total harmonic distortion (THD) of 105 dB can be acquired at 125 MSample/s.

On the design of a power conversion circuit

A kind of power conversion circuit, which converts positive voltage into negative one is presented according to the principle of negative voltage charge pump, so the DC output voltage is doubled. Factors affecting the speed and accuracy of MOS switches are fully considered, and a charge pump with MOS switches working in linear region is designed, avoiding the problem of threshold voltage drop. By single positive power supply, a non-overlapping clock is generated skillfully by changing switching threshold voltage of the inverters, to drive the MOS switches correctly with positive and negative voltage. The simulation results based on CMOS 0.35 mum technology show that, at 1 MHz refresh frequency, the circuit converts +1.5 V to -1.5 V, with error less than 0.2%, and setup time less than 20 mus. Besides, the circuit is less limited by the supply voltage and refresh frequency, and is not sensitive to the variations of process.

A novel gain error background calibration algorithm for time-interleaved ADCs

This paper presents a background calibration technique for gain error in Time-interleaved (TI) analog-to-digital converters (ADCs). The presented calibration technique is based on statistical characteristics of the input signal and error information can be obtained by analyzing the statistical properties of the input signal. Compared with conventional calibration algorithm, the presented calibration in this paper has low hardware resource consumption and no restriction on the input signal frequency, and can be extended to arbitrary number of channels. Simulation of the 8-bit 5-channel TIADCs with MATLAB shows that with gain error in the range of ±5% Vref, SNR of the output signal of the TIADCs is only 29.8dBc and reach 47.9dBc after calibration. The TIADCs performance is enhanced significantly by using this calibration algorithm.

Design of low-jitter clock duty cycle stabilizer in high-performance pipelined ADC

This paper introduces a design of clock duty cycle stabilizer (DCS) for high-speed pipelined ADC, and analyses the internal parameters on the impact of the circuit performance. Circuit module includes programmable clock input buffer, clock synthesizer, duty cycle detection circuit and nonoverlapping clock generation circuit. The circuit and layout are achieved by 0.18 μm CMOS 1P5M Mixed Signal process. The Cadence Spectre post-simulation results show: The circuit can work for a wide frequency range from 20MHz to 250MHz; duty cycle accuracy of (50±0.25) %, in the 250MHz input frequency, the RMS jitter is 53 fs. The measured performance shows it can work with high speed, high precision and low jitter characteristics, being not strictly requirement on the input clock signal, nonoverlapping time controllable.