Honyih Tu

A 0.66e − rms temporal-readout-noise 3D-stacked CMOS image sensor with conditional correlated multiple sampling (CCMS) technique

A conditional correlated multiple sampling (CCMS) technique for low noise CMOS image sensor (CIS) is proposed to reduce noise and address low frame rate issue caused by the conventional correlated multiple sampling (CMS) technique. An 8Mpixel 3D-stacked CIS with 1.1um pixel pitch is designed and verified. Measurement results show this technique can achieve 0.66e-rms at 36.1 kHz A/D sampling rate per pixel with analog gain at 16 and 5-times multiple sampling. The resulting DNL is within -0.49/+0.45LSB.

CMOS Image Sensor Random Telegraph Noise Time Constant Extraction From Correlated To Uncorrelated Double Sampling

A new method for on-chip random telegraph noise (RTN) characteristic time constant extraction using the double sampling circuit in an 8.3 Mpixel CMOS image sensor is described. The dependence of the measured RTN on the time difference between the double sampling and the key equation used for time constant extraction are derived from the continuous time RTN model and the discrete event RTN model. Both approaches lead to the same result and describe the data reasonably well. From the detailed study of the noisiest 1000 pixels, we find that about 75% to 85% of them show the signature of a single-trap RTN behavior with three distinct signal levels, and about 96% of the characteristic time constants fall between 1 μs and 500 μs with the median around 10 μs at room temperature.

A peripheral switchable 3D stacked CMOS image sensor

A 1.1 um pitch pixel array fabricated by 45 nm 3D stacked technology, can be switched to peripheral circuits on same wafer or to other stacked wafer for process and signal integrity verification. It supports through silicon connection or direct connection to increase the flexibility by separating pixel array and sensing circuit. The novel wide operation range VCO and low power serializer are implemented to reduce the total power and noise.

6.8 A 1.5V 33Mpixel 3D-stacked CMOS image sensor with negative substrate bias

3D stacking and computational imaging are two major driving forces for CMOS image sensors. In addition, 3D stacking separates pixel array and peripheral circuits. As such, computational imaging blocks (stereo vision, array camera, reconfigurable instruction cell array, etc.) can integrate with sensor circuits while leveraging advanced CMOS technologies including FinFET. To accommodate this trend, we need to design blocks such as comparators, readouts, transmitters, and PLLs, using digital architectures in logic processes with a minimum number of resistors and capacitors. Achieving 100% array-to-chip area ratio is an ultimate goal of 3D CIS. For this reason, all peripheral circuits must be under the pixel array. However, row and column circuits may overlap at the corner if both pitches are equal to pixel pitch. To avoid this issue, we make row and pixel pitch the same, and shrink column pitch to 82% to spread the column signal to array width using the “river routing” tools introduced for display-driver ICs, as shown in Fig. 6.8.1. The 3D stacking technology we apply [1] is top-metal face-to-face, and it can put 3D connections under a backside-illuminated pixel array. Therefore it increases array-to-chip area ratio comparing with a TSV chip that uses area outside the pixel array. This chip demonstrates the 3D connections at the center of the uniform 33Mpixel array and seamless image readout using 4 identical 8.3Mpixel circuit units. Instead of developing new circuitry, we can combine 16 compact units for 133Mpixel at the same frame rate and save the extra driving power.

Statistical Analysis of the Random Telegraph Noise in a 1.1 μm Pixel, 8.3 MP CMOS Image Sensor Using On-Chip Time Constant Extraction Method

A study of the random telegraph noise (RTN) of a 1.1 μm pitch, 8.3 Mpixel CMOS image sensor (CIS) fabricated in a 45 nm backside-illumination (BSI) technology is presented in this paper. A noise decomposition scheme is used to pinpoint the noise source. The long tail of the random noise (RN) distribution is directly linked to the RTN from the pixel source follower (SF). The full 8.3 Mpixels are classified into four categories according to the observed RTN histogram peaks. A theoretical formula describing the RTN as a function of the time difference between the two phases of the correlated double sampling (CDS) is derived and validated by measured data. An on-chip time constant extraction method is developed and applied to the RTN analysis. The effects of readout circuit bandwidth on the settling ratios of the RTN histograms are investigated and successfully accounted for in a simulation using a RTN behavior model.