Horng-Dar Lin

Algorithms and architectures for concurrent Viterbi decoding

The sequential nature of the Vitterbi algorithm places an inherent upper limit on the decoding throughput of the algorithm in a given integrated circuit technology and thereby restricts its applications. Three methods of generating inherently unlimited concurrency in Viterbi decoding, for both controllable and uncontrollable shift register processes and Markov processes, are described. Concurrent decoders using these methods can apply high-throughput architectures with an overhead of pipeline latches or parallel hardware. A feasible method for bypassing the hardware limit is also proposed for decoding at an arbitrarily high as well as variable throughput. The proposed methods make real-time Viterbi decoding in the gigabit-per-second range feasible for convolutional and trellis codes.<<ETX>>

Designing a high-throughput VLC decoder. I. Parallel decoding methods

For pt.I see ibid, vol.2, no.2, p.187, 1992, For applications in graphic computers, image and video composition, high-definition television (HDTV), and optical fiber networks, Huffman-coded images need to be reconstructed at a high throughput rate. Part I showed several architectural and architecture-specific optimization techniques. However, due to the recursion within the reconstruction algorithm, the achievable throughput rate for a given decoding architecture in a given IC technology is limited. The authors propose various concurrent decoding methods to relax the throughput limit by using parallel or pipelined hardware. These methods are simple, effective, flexible, and applicable to general decoder architectures. Unlimited concurrency can be achieved at the expense of additional latency, the overhead is low, and the complexity increases linearly with the throughput improvement. It is believed that the proposed methods and architectures make it possible to reconstruct arbitrarily high resolution Huffman-coded images and video in real time with current electronics. >

Finite state machine has unlimited concurrency

General methods for introducing concurrency, by which the throughput of finite-state machines (FSM) can be improved at the expense of latency, are described. The methods are applicable to software and hardware implementation using parallelism or pipelining and demonstrate that there is no theoretical limit to concurrency in a discrete-time finite-state machine. The methods can arbitrarily improve the iteration bound of discrete-time FSMs with low hardware overhead. They are efficient when the state size is finite and moderate, as in controllers, encoders, source decoders, etc. When the state size is large and the recurrence is not a closed-form function of specific classes, the methods cannot be applied directly. Another limitation is the latency induced by the block methods. In most cases, this is not a problem because the overall cost and throughput rather than latency are at stake. >

Improving the iteration bound of finite state machines

A description is given of a general approach to improve beyond the given iteration bound the speed of an arbitrary synchronous finite-state machine (FSM) or a discrete-time finite-state Markov process. The methods proposed can be implemented with pipelined arrays of simple hardware modules, achieving a throughput rate on the order of the reciprocal of a single-gate delay or latch setup time, whichever is limiting, at the expense of latency. Combining the pipelined arrays and modules in parallel further increases the throughput, which is theoretically unbounded. The implemented concurrent FSM is fully efficient and has minimal overhead, where the complexity grows only linearly with the speedup. The approach is practical for FSMs with a small number of states, or other special structures.<<ETX>>

Video composition methods and their semantics

A comparison is made of four modular composition methods suitable for pipeline architectures, including object-based and pel-based composition methods with absolute or relative ordering. For each composition method, it is shown what it does, what it means physically, and thus what limitation it imposes. The conclusion is that the object-based methods, although more efficient to describe video composition, are not completely general. A method is proposed to extend the generality of object-based composition while also retaining its efficiency in describing video composition.<<ETX>>

General in-place scheduling for the Viterbi algorithm

It is shown how to find in-place schedules for all kinds of trellises, including periodic and aperiodic in-place schedules. It is also shown how to verify the existence of aperiodic and periodic in-place schedules. With this in-place scheduling, one can improve data locality and thus reduce interprocessor communication bandwidths. This means a smaller overhead in chip routing area or communication cycles. The methods also apply to general parallel processing with trellis-like computational graphs.<<ETX>>

High throughput reconstruction of Huffman-coded images

The Huffman code is an efficient noiseless coding method for images, video, and other applications. For applications in graphic computers, high-definition televisions (HDTV), and optical fiber networks, Huffman-coded images need to be reconstructed at a high throughput rate. Due to the recursion within the reconstruction algorithm, the achievable throughput rate in a given IC technology is limited by the iteration bound. Methods of relaxing the iteration bound of the reconstruction process, thus increasing the concurrency in the decoding process, are proposed. These methods are simple, effective, and flexible. Unlimited concurrency can be achieved at the expense of additional latency. The incurred overhead is very low, and the complexity increases only linearly with the achieved throughput improvement.<<ETX>>

Parallel Viterbi decoding methods for uncontrollable and controllable sources

The parallel Viterbi decoding is discussed for two different cases: uncontrollable sources and controllable sources. For general, uncontrollable Markov processes, a previously known parallel method is extended to a hierarchical parallel decoding approach, which achieves a lower latency. For controllable Markov sources in telecommunications applications, new parallel decoding methods are obtained by controlling the source processes in appropriate ways. The focus is on the parallel decoding methods for controllable sources because these methods have zero processing overhead. Because the methods modify the coding process, they bring positive changes to framing and negative changes to latency and code performance. However, one can adjust the parameters of the methods to make the degradation negligible. Because of their low overhead, the methods are most attractive for high-speed decoders for convolutional and trellis codes, and they are also applicable to other sequential algorithms for suboptimal decoding and estimation of complex Markov sources. >

Architectural techniques for eliminating critical feedback paths

The authors demonstrate architectural techniques, for small-state feedback circuits that significantly improve the throughput without requiring circuit design efforts or advanced technologies. The method is flexible in terms of achievable implementations and speedups. The authors discuss a new high-throughput solution for systems with finite-level feedback values. As an example, the authors consider coding and signal processing systems for optical communications, which usually have very simple feedback. The authors demonstrate the method by realizing a 2 micron CMOS layout of a bimode 3B4B line coder. Simulation results show that, using standard cell design, the chip achieves a coding rate of 1.4 Gb/s. Other design options are discussed. >

A hybrid pipelined path-searching architecture for multiple communications applications

A high-throughput architecture that can search for the shortest path within a graph is proposed. The architecture can decode any data encoded with a finite state machine or data encrypted in a dynamic trellis code, and also serve as a specialized processor for other searching and matching applications. The proposed retargetable architecture is suitable for futuristic workstations equipped with wireless access, basic voice recognition, and high speed data services. Balance between flexibility and hardware efficiency is achieved by an integrated design of architecture, in-place scheduling, and concurrent algorithms.<<ETX>>