David G. Messerschmitt

Synchronous data flow

Data flow is a natural paradigm for describing DSP applications for concurrent implementation on parallel hardware. Data flow programs for signal processing are directed graphs where each node represents a function and each arc represents a signal path. Synchronous data flow (SDF) is a special case of data flow (either atomic or large grain) in which the number of data samples produced or consumed by each node on each invocation is specified a priori. Nodes can be scheduled statically (at compile time) onto single or parallel programmable processors so the run-time overhead usually associated with data flow evaporates. Multiple sample rates within the same system are easily and naturally handled. Conditions for correctness of SDF graph are explained and scheduling algorithms are described for homogeneous parallel processors sharing memory. A preliminary SDF software system for automatically generating assembly language code for DSP microcomputers is described. Two new efficiency techniques are introduced, static buffering and an extension to SDF to efficiently implement conditionals.

Static Scheduling of Synchronous Data Flow Programs for Digital Signal Processing

Large grain data flow (LGDF) programming is natural and convenient for describing digital signal processing (DSP) systems, but its runtime overhead is costly in real time or cost-sensitive applications. In some situations, designers are not willing to squander computing resources for the sake of programmer convenience. This is particularly true when the target machine is a programmable DSP chip. However, the runtime overhead inherent in most LGDF implementations is not required for most signal processing systems because such systems are mostly synchronous (in the DSP sense). Synchronous data flow (SDF) differs from traditional data flow in that the amount of data produced and consumed by a data flow node is specified a priori for each input and output. This is equivalent to specifying the relative sample rates in signal processing system. This means that the scheduling of SDF nodes need not be done at runtime, but can be done at compile time (statically), so the runtime overhead evaporates. The sample rates can all be different, which is not true of most current data-driven digital signal processing programming methodologies. Synchronous data flow is closely related to computation graphs, a special case of Petri nets. This self-contained paper develops the theory necessary to statically schedule SDF programs on single or multiple processors. A class of static (compile time) scheduling algorithms is proven valid, and specific algorithms are given for scheduling SDF systems onto single or multiple processors.

Simulation of multipath impulse response for indoor wireless optical channels

A recursive method for evaluating the impulse response of an indoor free-space optical channel with Lambertian reflectors is presented. The method, which accounts for multiple reflections of any order, enables accurate analysis of the effects of multipath dispersion on high-speed indoor optical communication systems. A simple algorithm for computer implementation of the technique and computer simulation results for both line-of-sight and diffuse transmitter configurations are also presented. In both cases, it is shown that reflections of multiple order are a significant source of intersymbol interference. Experimental measurements of optical multipath, which help verify the accuracy of the simulations, are discussed. >

Manipulation and compositing of MC-DCT compressed video

Many advanced video applications require manipulations of compressed video signals. Popular video manipulation functions include overlap (opaque or semitransparent), translation, scaling, linear filtering, rotation, and pixel multiplication. We propose algorithms to manipulate compressed video in the compressed domain. Specifically, we focus on compression algorithms using the discrete cosine transform (DCT) with or without motion compensation (MC). Such compression systems include JPEG, motion JPEG, MPEG, and H.261. We derive a complete set of algorithms for all aforementioned manipulation functions in the transform domain, in which video signals are represented by quantized transform coefficients. Due to a much lower data rate and the elimination of decompression/compression conversion, the transform-domain approach has great potential in reducing the computational complexity. The actual computational speedup depends on the specific manipulation functions and the compression characteristics of the input video, such as the compression rate and the nonzero motion vector percentage. The proposed techniques can be applied to general orthogonal transforms, such as the discrete trigonometric transform. For compression systems incorporating MC (such as MPEG), we propose a new decoding algorithm to reconstruct the video in the transform domain and then perform the desired manipulations in the transform domain. The same technique can be applied to efficient video transcoding (e.g., from MPEG to JPEG) with minimal decoding. >

Static rate-optimal scheduling of iterative data-flow programs via optimum unfolding

Rate-optimal compile-time multiprocessor scheduling of iterative dataflow programs suitable for real-time signal processing applications is discussed. It is shown that recursions or loops in the programs lead to an inherent lower bound on the achievable iteration period, referred to as the iteration bound. A multiprocessor schedule is rate-optimal if the iteration period equals the iteration bound. Systematic unfolding of iterative dataflow programs is proposed, and properties of unfolded dataflow programs are studied. Unfolding increases the number of tasks in a program, unravels the hidden concurrently in iterative dataflow programs, and can reduce the iteration period. A special class of iterative dataflow programs, referred to as perfect-rate programs, is introduced. Each loop in these programs has a single register. Perfect-rate programs can always be scheduled rate optimally (requiring no retiming or unfolding transformation). It is also shown that unfolding any program by an optimum unfolding factor transforms any arbitrary program to an equivalent perfect-rate program, which can then be scheduled rate optimally. This optimum unfolding factor for any arbitrary program is the least common multiple of the number of registers (or delays) in all loops and is independent of the node execution times. An upper bound on the number of processors for rate-optimal scheduling is given. >

Pipeline interleaving and parallelism in recursive digital filters. I. Pipelining using scattered look-ahead and decomposition

A look-ahead approach (referred to as scattered look-ahead) to pipeline recursive loops is introduced in a way that guarantees stability. A decomposition technique is proposed to implement the nonrecursive portion (generated due to the scattered look-ahead process) in a decomposed manner to obtain concurrent stable pipelined realizations of logarithmic implementation complexity with respect to the number of loop pipeline stages (as opposed to linear). The upper bound on the roundoff error in these pipelined filters is shown to improve with an increase in the number of loop pipeline stages. Efficient pipelined realizations are studied of both direct-form and state-space-form recursive digital filters. Based on the scattered look-ahead technique, fully pipelined and fully hardware efficient linear bidirectional systolic arrays for recursive digital filters are presented. The decomposition technique is extended to time-varying recursive systems. >

Nonlinear Echo Cancellation of Data Signals

This paper describes a new technique for implementing an echo canceller for full-duplex data transmission (such as in digital subscriber loops and volceband data sets). The canceller can operate in spite of time-invariant nonlinearities in the echo channel or in the implementation of the echo canceller itself (such as in the D/A converters). The basic structure of the linear echo canceller is not changed, but taps are simply added to account for the nonlinearity. The number of taps which must be added depends on the degree of nonlinearity which must be compensated. Numerical results based on computer simulation are given which show that typical nonlinearities encountered in MOS D/A converters can be compensated by a relatively small number of taps added to the linear echo canceller, and substantial improvement in the cancellation results.

Resynchronization of motion compensated video affected by ATM cell loss

Techniques for resynchronizing motion-compensation-based coders and strategies for the recovery of lost motion vectors are discussed. Leaky-difference resynchronization yields perceptually pleasing video sequences even at fairly high cell loss rates. Future study is needed to determine optimal data-dependent or network-state-dependent conditional resynchronization strategies. Lost motion vectors can be predicted accurately with either the median of intraframe neighboring vectors or the corresponding past-frame vector. The replacement of lost motion vectors with estimates such as these can significantly improve the quality of video affected by cell loss.<<ETX>>

A low-noise chopper-stabilized differential switched-capacitor filtering technique

Describes the implementation of a wide dynamic range voiceband switched-capacitor filter using a differential chopper-stabilized configuration. The noise behavior of switched-capacitor filters is discussed qualitatively, and the effects of the chopper stabilization on the noise performance is analyzed. Experimental results from a fifth-order low-pass voiceband prototype are presented.

Automatic synthesis of asynchronous circuits from high-level specifications

The authors construct a processor design approach that does not require the distribution of a clocking signal. To facilitate design of processors that use fully asynchronous components, the first step is to design hazard-free asynchronous interconnection circuits. To this end, a deterministic algorithm was developed to synthesize asynchronous interconnection circuits from high-level specifications. This approach systematically designs correct asynchronous interconnection circuits with the weakest possible constraints and minimal overhead. The authors are primarily concerned with the synthesis of nonmetastable circuits, even though the procedure is also valid of metastable circuit synthesis. The synthesized logic is hazard-free and guaranteed to have the fastest operation according to a behavioral specification. A high-level description is used to specify circuit behavior, not only for a simpler input format, but also as a basis for determining the final optimum designs. Automatic synthesis and the ability to localize the timing considerations reduce design effort when systems become complex. >