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Dive into the research topics where Horst H. Berger is active.

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Featured researches published by Horst H. Berger.


Solid-state Electronics | 1972

Models for contacts to planar devices

Horst H. Berger

Abstract Two basic models for rectangular contacts to planar devices, the Kennedy-Murley Model (KMM) and the Transmission Line Model (TLM) are discussed and compared. The KMM does not take into account the interface resistance between metal and semiconductor, whereas the TLM disregards the vertical structure of the semiconductor layer. An extension of the TLM is derived (ETLM), which approximately considers this vertical structure. KMM and TLM thus appear as special cases of the ETLM. The calibration of the latter on the KMM then yields a simple quantitative criterion for the applicability of the KMM or the pure TLM. Measurement results on typical aluminum-silicon contacts are described satisfactorily by the (E)TLM. Concurrently with the applicability criterion, the KMM proves inadequate for these contacts due to the disregard of interface resistance. Conclusions are derived from the TLM pertaining to current distribution over the contact area and to contact resistance. In particular, the contacts are classified according to their operation mode. Finally, the TLM approach is applied also to circular contacts.


IEEE Transactions on Electron Devices | 1979

The lateral p-n-p transistor—A practical investigation of the DC characteristics

Horst H. Berger; U. Dreckmann

The dc characteristics of the lateral p-n-p transistor are investigated with the goal of providing an uncomplicated but accurate description that considers the practical needs of the device and circuit designer. An experimental step-by-step analysis of collector- and base-current components shows that a one-dimensional model describes the device adequately. The model parameters are closely related to process parameters and device geometry allowing quick assessments of layouts and processes. In particular, a comparison of various emitter geometries is given, showing among other facts the adverse effect of unnecessarily large emitter contact holes. Of the mechanisms determining the base current, volume and surface recombination in the intrinsic base were found to be insignificant. Instead, an additional component, the vertical diffusion of holes out of the intrinsic base, has been experimentally verified. The main contribution to base current, however, is the current across the emitter bottom junction. High-level injection is considered in the collector current by using a modification of Chous equations. Gummel-Poon knee voltages have been determined for various dopings and basewidths. Our experiments show that the knee voltage depends on basewidth, which goes beyond Chous description.


IEEE Transactions on Electron Devices | 1979

An investigation of the intrinsic delay (speed limit) in MTL/I 2 L

Horst H. Berger; Klaus Helwig

This paper identifies and analyzes the main mechanisms that determine the intrinsic delay (speed limit) of todays MTL/I2L devices. Experimental devices have been fabricated with different epitaxial thicknesses to find out to what extent the charge storage can be reduced by shallow epitaxy. Such a shallow-epitaxy device is investigated using computer simulation. Hereby, the injection model is used, into which new charge storage parameters are introduced. According to the analysis, the majority of the stored mobile charge is associated with the bottom junction of the n-p-n transistor part, while the charges in the p-n-ps intrinsic base are minor. However, the lateral p-n-p transistor contributes to the intrinsic delay by its high-level-injection current gain falloff. Furthermore, the significance of high intrinsic base sheet resistance of the n-p-n transistor for high speed is pointed out. Using the insight gained, a device is laid out that assumes only existing technologies, yet in the simulation yields intrinsic delays as low as 2 ns for a fan-out of 4.


Solid-state Electronics | 1973

A new static shift register with dynamic transfer

Siegfried K. Wiedmann; Horst H. Berger

Abstract A new shift register of extremely low d.c. standby power has been implemented in a simplified bipolar transistor technology using 4 mask steps up to metallization and 2 diffusions only. The bit density is 250 bit/mm 2 with 5 μm line dimensions, the standby power 0·1 μW/bit and the cycle time 150 nsec at 150 μW/bit. The shift register features a new operation principle: In standby, it is truly static, whereas for shifting the memory operates dynamically utilizing the effect that a dynamically unbalanced flip-flop switches into a definite state. The dynamic charge unsymmetry originates from the state of the previous cell and is shifted to the next one after each clock cycle.


Archive | 1971

Monolithic semiconductor circuit for a logic circuit concept of high packing density

Horst H. Berger; Siegried K. Wiedmann


Archive | 1973

MULTILAYERED VERTICAL TRANSISTOR HAVING REACH-THROUGH ISOLATING CONTACTS

Horst H. Berger; Siegfried K. Wiedmann


Archive | 1976

Circuit arrangement for operating a semiconductor memory system

Horst H. Berger; Klaus Heuber; Wilfried Klein; Knut Najmann; Siegfried K. Wiedmann


Archive | 1972

MONOLITHIC SEMICONDUCTOR MEMORY

Horst H. Berger; Sigfried K Wiedmann


Microelectronics Journal | 1976

Advanced Merged Transistor Logic by Using Schottky Junctions

Horst H. Berger; Siegfried K. Wiedmann


Archive | 1973

Monolithically integrable digital basic circuit

Horst H. Berger; Siegfried K. Wiedmann

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