Siegfried K. Wiedmann

Injection-coupled memory: A high-density static bipolar memory

The design of a new static bipolar memory comparable with dynamic FET storages in density, but superior in performance and power dissipation is discussed. The concept of direct minority carrier injection is utilized for both the cell current supply and the coupling to the read/write lines. This has led to an extremely high degree of device integration resulting in a cell size of 3.1 mil/SUP 2/ using a standard buried layer process with 5-/spl mu/ line dimensions and single layer metallization. Investigations on exploratory chips containing small arrays have fully verified the feasibility. The cells have been operated at an extremely small d.c. standby power of below 100 nW. For a 4K b chip of about 160/spl times/150 mil/SUP 2/, an access time around 50 ns can be projected from the measurements simulating a 64/spl times/64 bit array. An extrapolation of the memory cell layout with oxide isolation and self-aligned N/SUP +/ contacts has resulted in a 1.1-mil/SUP 2/ cell with 5-/spl mu/ line dimensions.

Small-size low-power bipolar memory cell

A d.c.-stable random-access memory (RAM) cell employing n-p-n and p-n-p transistors has been designed in a concurrent circuit-layout approach. Test chips with 2×3 arrays have been processed in a standard bipolar technology. Due to the merging of devices, the area required for a cell is only 14 mil2. The cells have been operated at an extremely low d.c. standby power of less than 0.1 μW/cell. In spite of this low standby power, an array access time of 10 ns has been measured on a simulated 512-bit array in a pulsed power mode.

Potential of bipolar complementary device/Circuit technology

Bipolar complementary transistor logic circuits have been very little explored. The main reason certainly is that the bipolar transistor as a current controlled device is not as suited for such circuit applications as the voltage controlled MOSFET. After briefly explaining the major obstacles for CMOS-like bipolar complementary circuits and deriving the stringent device/technology prerequisites for any practical realisation, the recently proposed Charge Buffered Logic as a unique bipolar complementary circuit concept is described. Its potential for high speed at microwatt DC power, the key device parameters, and critical design aspects are discussed.

Subnanosecond Self-Aligned I/sup 2/L/MTL Circuits

A self-aligned I/sup 2/L/MTL technology featuring collectors doped from and contacted by polysilicon, self-aIigned collector and base contact edges, and metal-interconnected bases is described. Experimental ring-oscillator circuits designed with 2.5-/spl mu/m design roles and fabricated with this technology exhibit gate delays as small as 0.8 ns at lC = 100 -/spl mu/A for fan-in = 1 and fan-out = 3. Increased wiring flexibility and improved circuit density are inherent advantages of this self-aligned technology.

A novel saturation control in TTL circuits

A novel technique of saturation control in TTL and other saturated logic circuits is described and analyzed. The approach is not only fully compatible with standard bipolar transistor technology, but lends itself to integration. The device parameter tracking on a chip is utilized to suitably bias a feedback saturation control transistor so that the stored charge of a TTL gate output transistor is reduced by typically two orders of magnitude. Thus, the turn-off switching time is significantly decreased without noticeably affecting the turn-on delay time. The performance improvement is close to that achieved by the well-known Schottky diode clamp approach; however, the novel technique offers advantages in noise margin, control of down-level output voltage, and processing. The effectiveness of the proposed technique has been verified theoretically by computer circuit analysis and experimentally by bench setup measurements.

Sub-nanosecond self-aligned I 2 L/MTL circuits

This paper describes a self-aligned approach to the I²L/MTL technology. Experimental ring oscillator circuits designed with 2.5 µm design rules and fabricated with this technology show a measured 0.9 ns gate delay at I<inf>c</inf>= 70 µA (fan-in=1, fan-out=3).

High-density static bipolar memory

A static bipolar memory approach with a 3.1-mil2cell in standard technology affording a 4k-bit chip with 50-ns access time at 0.1 μW/bit standby power will be described.

High-speed split-emitter I/sup 2/L/MTL memory cell

Describes a novel circuit/device approach that overcomes the performance drawback of the injection-sensed I/SUP 2/L/MTL memory cell cited in a 16-kbit static MTL RAM (see IEEE ISSCC Dig. Tech. Papers, p.222-4, 1980). As a result, a compact memory cell with extremely low DC standby power in the nanowatt range and with read/write times below 5 ns is achieved. This has been verified by experimental investigations on small test arrays. They have been fabricated with an advanced process featuring a p-polysilicon-base self-alignment scheme and a double-diffused p-n-p structure. In addition, computer circuit simulations have been performed that show the read delay sensitivities in large arrays. Based on these results, an access time of less than 25 ns is projected for a 16-kbit MTL RAM.

A new static shift register with dynamic transfer

Abstract A new shift register of extremely low d.c. standby power has been implemented in a simplified bipolar transistor technology using 4 mask steps up to metallization and 2 diffusions only. The bit density is 250 bit/mm 2 with 5 μm line dimensions, the standby power 0·1 μW/bit and the cycle time 150 nsec at 150 μW/bit. The shift register features a new operation principle: In standby, it is truly static, whereas for shifting the memory operates dynamically utilizing the effect that a dynamically unbalanced flip-flop switches into a definite state. The dynamic charge unsymmetry originates from the state of the previous cell and is shifted to the next one after each clock cycle.

Super-integrated bipolar memory device for high-density, low-power storage

A novel bipolar memory device for high-density, low power read/write storages has been developed, fabricated and analyzed. It has been operated at a standby power of 100 nanowatts and can be conveniently switched to currents larger by orders of magnitude to speed up the read and write operation. The cell size of 4 mil2achieved by conventional processing with a 3µ epitaxial layer thickness and a minimum metal line width of 0.25 mils (spacing 0.15 mil) allows at least 2000 bits/chip. Despite this high density an access/cycle time of about 60/150ns has been projected from array simulation measurements on single devices. In contrast to other approaches in this bit density range, this statically stable device does not require any refresh operation.