Hossein Sarbishaei

ESD Protection Device and Circuit Design for Advanced CMOS Technologies

ESD Protection Device and Circuit Design for Advanced CMOS Technologies is intended for practicing engineers working in the areas of circuit design, VLSI reliability and testing domains. As the problems associated with ESD failures and yield losses become significant in the modern semiconductor industry, the demand for graduates with a basic knowledge of ESD is also increasing. Today, there is a significant demand to educate the circuits design and reliability teams on ESD issues. This book makes an attempt to address the ESD design and implementation in a systematic manner. A design procedure involving device simulators as well as circuit simulator is employed to optimize device and circuit parameters for optimal ESD as well as circuit performance. This methodology, described in ESD Protection Device and Circuit Design for Advanced CMOS Technologies has resulted in several successful ESD circuit design with excellent silicon results and demonstrates its strengths.

A transient power supply ESD clamp with CMOS thyristor delay element

A novel clamp is presented that uses a CMOS thyristor to turn on the clamp at the ESD event. This clamp is immune to false triggering and power supply noise. Furthermore, the instability of clamps is analyzed and the new clamp is shown to have immunity to oscillation.

Novel gate and substrate triggering techniques for deep sub-micron ESD protection devices

As technology feature size is reduced, ESD becomes the dominant failure mode due to lower gate oxide breakdown voltage. In this paper, the effectiveness of new gate and substrate triggering techniques has been investigated to lower the trigger voltage of the LVTSCR and MOSFET based ESD protection circuits using 2D simulations and HBM/TLP measurements. The simulation results show that the using these techniques reduces the ESD triggering voltage by 63 and 44% for MOSFET-based and LVTSCR-based ESD structures, respectively, under 2 kV HBM ESD stress. The effectiveness of proposed gate and substrate triggering techniques is also confirmed by the HBM and TLP measurements.

Optimizing Circuit Performance and ESD Protection for High-Speed Differential I/Os

Impact of ESD protection devices on circuit operation is very important in gigahertz applications. In this paper, the impact of different ESD protection methodologies on CML drivers is discussed. ESD protection is provided using MOSFET and SCR devices. Study of the interaction between driver and ESD protection circuit shows that jitter is very sensitive to parasitics of ESD protection circuits. Furthermore, an analysis shows that substrate-triggering has less impact on jitter compared to gate-coupling.

Analysis and design of LVTSCR-based EOS/ESD protection circuits for burn-in environment

As technology feature size is reduced, ESD becomes one of the dominant failure modes due to the lower gate oxide breakdown voltage. Also, the holding voltage of LVTSCR devices is reduced with operating temperature increase. As a result, during stress testing (burn-in), the risk of latch-up in LVTSCR is extremely high. In this paper, a new latch-up free LVTSCR-based protection circuit is proposed. It can be reliably used in sub-0.18 /spl mu/m CMOS technologies and burn-in environment. The proposed ESD circuit has higher holding voltage by 1.5/spl times/ than the conventional LVTSCR structure at burn-in temperature. Under 3 kV HBM ESD stress, the developed LVTSCR-based protection circuit has the voltage peak less than the conventional LVTSCR structure and GG-MOSFET by 2/spl times/ and 1.25/spl times/, respectively.

Adarlington-based SCR ESD protection device for high-speed applications

Silicon controlled rectifiers (SCRs) are used extensively in high frequency applications. To reduce their first breakdown voltage, they are used with different triggering mechanisms. In this paper, a novel ESD protection device is proposed that can reduce the first breakdown voltage of SCR to 3V without any extra triggering devices.

ESD protection circuit for 8.5Gbps I/Os in 90nm CMOS technology

In this paper we designed an ESD protected CML driver for 8.5Gbps data rate. ESD protection for this circuit is provided with DSCR. A detailed analysis is done on the impact of ESD protection on performance of the driver. It is shown that DSCR offers up to 2.7kV HBM protection with very small impact on performance of the driver.

ESD protection for mixed-signal circuits — design or test problem?

In spite of significant progress during last couple of decades, ESD still affects production yields, manufacturing costs, product quality, reliability and profitability. The objective of an ESD protection circuit is to create a harmless shunting path for the static electricity before it damages the sensitive electronic circuits. As the devices are continuously scaling down, while ESD energy remains the same, VLSIs become more vulnerable to ESD stress. This higher susceptibility to ESD damage is due to thinner gate oxides and shallower junctions. Furthermore, higher operating frequency of the scaled technologies enforces lower parasitic capacitance of the ESD protection circuits. As a result, increasing the robustness of the ESD protection circuits with minimum additional parasitic capacitance is the main challenge in state of the art CMOS processes. In this paper a general methodology to design ESD protection circuits and devices is discussed. This method is used to tackle some of the main challenges facing ESD designers in modern technologies.