Houpeng Chen

An 8-Mb Phase-Change Random Access Memory Chip Based on a Resistor-on-Via-Stacked-Plug Storage Cell

In this letter, an 8-Mb phase-change random access memory (PCRAM) chip has been developed in a 130-nm 4-ML standard CMOS technology based on a Resistor-on-Via-stacked-Plug (RVP) storage cell structure. This phase-change resistor is formed after CMOS logic fabrication. PCRAM can be embedded without changing any logic device and process. The memory cell selector is implemented by a standard 1.2-V nMOS device. The currents of the set and reset operations are 0.4 and 2.2 mA, respectively. The best endurance is over 1010 cycles.

RESET Distribution Improvement of Phase Change Memory: The Impact of Pre-Programming

Some nonvolatile phase change memory (PCM) cells with 80-nm heating electrodes are found very difficult to RESET at 3 mA, which directly affects the RESET distribution of the PCM. The large crystal grains with hexagonal structure in the active phase change area, discovered by transmission electron microscope, are the major reason. One preprogramming testing method is introduced, and the resistance distributions of the PCM cells before and after preprogramming are presented. Results show that the large hexagonal crystal grains have been eliminated, thus the resistance distributions have been greatly improved after preprogramming.

Optimization of 40-nm Node Epitaxial Diode Array for Phase-Change Memory Application

A numerical model of an epitaxial (EPI) diode array for next-generation memory device application, including phase-change memory, has been presented. According to a diode array process scheme and technology computer-aided design (TCAD) simulation results, a quasi-physical model with a buried n+ layer dosage, EPI layer thickness, and breakdown voltage (BVD) correlation is proposed to improve electrical performance. From the optimal silicon-based results, a 16×16 diode array shows a drive current density of ~56.6 mA/μm2, a BVD of ~8 V, a Jon/Joff ratio of ~109, and crosstalk immunity. Additionally, this calibrated physical model can be applied in the next generation of silicon-based fabrication with parameters extraction.

Optimization of periphery circuits in a 1K-bit PCRAM chip for highly reliable write and read operations

A 1K-bit phase change random access memory (PCRAM) with improved periphery circuits for better reliable operations has been successfully developed in 130 nm CMOS technology. A flexible write driver is proposed to provide a novel continuous step-down pulses by studying programming strategies while a reliable read circuit is designed by investigating the special transition characteristics of PCRAM, leading to an effective write operation and a non-destructive read operation without any additional changes of the storage states. In addition, a large sense margin has been achieved and the read results corresponding well with the write operations, which demonstrate the influences of technology variations have been considerably decreased with the proposed periphery circuits.

Methods to speed up read operation in a 64 Mbit phase change memory chip

A 64Mbit phase change memory chip is fabricated in 40 nm CMOS technology. An improved fully-differential sense amplifier with a bias voltage instead of the reference resistor branch is proposed to diminish the chip area. The transient response capability of the proposed sense amplifier is improved by removing the large parasitic capacitance of bit line in the feedback network. Smaller parasitic capacitance is also obtained by the separated programming and reading transmission gates to speed up the read operation. The hierarchical bit line architecture is used to reduce the length of bit line, and thus favorable read performance can be achieved.

A novel low-ripple charge pump for PCM

A switched capacitor charge pump applicable to phase change memory(PCM) is presented, which can provide a extra low ripple DC output of 5V with a maximum load condition of 10mA. For low output ripple and high power effiency, a novel operation mode is used. Compared with the conventional switched capacitor charge pump, the flying capacitor of the proposed charge pump is charged to Vo-VDD instead of VDD during the charge period(Vo is the prospective output voltage).In the discharge period, the flying capacitor is placed in series with the VDD to transfer energy to output, so the output voltage is regulated at Vo. A simulation was implemented for a DC input range of 2.8–4.4V in a SMIC standard 0.18um CMOS process, the result shows the new operation mode could regulate the output about 5V with a load conditon from 0 to 10mA, and the ripple voltage is lower than 3mV. The higest power effiency reaches 88%.

Enhanced 3 × VDD-tolerant ESD clamp circuit with stacked configuration

An enhanced 3 × VDD-tolerant ESD clamp circuit with stacked configuration was presented. Four transistors were added in this design to transfer bias voltages or ESD voltages. This circuit was simulated in 0.18 μm silicon-on-insulator (SOI) CMOS process and 28 nm HKMG CMOS technology. Spectre-simulation results showed that the ESD discharge current is increased by 2 times and the discharge current is decreased to nA magnitudes compared to the conventional circuit.

Optimization of Anomalous Cells with High SET Resistance in Phase Change Memory Arrays

The resistance distribution in the crystalline (SET) state of phase change memory (PCM) is experimentally investigated at the array level using an 8 Mbit test chip. The SET distribution shows a high resistance tail, which potentially affects the reading margin of the chip. To further understand the anomalous behaviors of these tail cells, the SET resistances are characterized in terms of the programming pulse current magnitude and duration. These tail cells are probably caused by incomplete crystallization of the inactive region of phase change material. Finally, an optimization approach of applying a direct current of 0.6 mA to these tail cells is proposed and experimentally verified.

Circuit design for 128Mb PCRAM based on 40nm technology

In this paper, a 128Mb phase change random access memory based on phase change Ge2Sb2Te5 alloy has been designed in 40nm 4 metal level CMOS technology. Memory cell is the dual trench epitaxial pn junction diode. According to the feature of the 1D1R memory cell structure, array architecture and chip architecture have been optimized. The read access time is 30ns in simulation. The layout area is 6.6mm × 3.8mm.

Design and analysis of a high-performance sense amplifier for phase-change memory

This paper presents a high-performance sense amplifier and its operation method for phase change memory (PCM). The proposed structure includes pre-charge circuit, judgment circuit, bias circuit and discharge circuit. Correspondingly, the read process includes four steps of pre-charging, relaxing, sensing and discharging. Simulation results show that the proposed sense amplifier can read out the cell status efficiently in 180ns both at low resistance (10K ohm) and high resistance (100K ohm) with the parasitic capacitance of 20pF. It will be used in 40nm 1Gbit phase change memory chip.