Daolin Cai

Ti10Sb60Te30 for phase change memory with high-temperature data retention and rapid crystallization speed

With a high crystallization temperature of 211 °C, Ti10Sb60Te30 phase change material exhibits a data retention of 10-yr at 137 °C, which is much better than that of usual Ge2Sb2Te5. No other phase is formed in Ti10Sb60Te30 film except hexagonal Sb2Te phase. For Ti10Sb60Te30-based phase change memory cell, as short as 6 ns electric pulse can fulfill the Set operation, demonstrating an extremely rapid crystallization speed of Ti10Sb60Te30. The programming cycles can reach 2.2 × 104 with very short Set/Reset pulses of 100 ns/50 ns.

An 8-Mb Phase-Change Random Access Memory Chip Based on a Resistor-on-Via-Stacked-Plug Storage Cell

In this letter, an 8-Mb phase-change random access memory (PCRAM) chip has been developed in a 130-nm 4-ML standard CMOS technology based on a Resistor-on-Via-stacked-Plug (RVP) storage cell structure. This phase-change resistor is formed after CMOS logic fabrication. PCRAM can be embedded without changing any logic device and process. The memory cell selector is implemented by a standard 1.2-V nMOS device. The currents of the set and reset operations are 0.4 and 2.2 mA, respectively. The best endurance is over 1010 cycles.

Understanding the early cycling evolution behaviors for phase change memory application

The RESET current of T-shaped phase change memory cells with 35 nm heating electrodes has been studied to understand the behavior of early cycling evolution. Results show that the RESET current has been significantly reduced after the early cycling evolution (1st RESET) operation. Compared the transmission electron microscope images, it is found that the hexagonal Ge2Sb2Te5 (GST) crystal grains are changed into the grains with face centered cubic structure after the early cycling evolution operation, which is taken as the major reason for the reduced RESET current, confirmed by a two-dimensional finite analysis and ab initio calculations.

Current Controlled Relaxation Oscillations in Ge2Sb2Te5-Based Phase Change Memory Devices*

The relaxation oscillation of the phase change memory (PCM) devices based on the Ge2Sb2Te5 material is investigated by applying square current pulses. The current pulses with different amplitudes could be accurately given by the independently designed current testing system. The relaxation oscillation across the PCM device could be measured using an oscilloscope. The oscillation duration decreases with time, showing an inner link with the shrinking threshold voltage Vth. However, the relaxation oscillation would not terminate until the remaining voltage Von reaches the holding voltage Vh. This demonstrates that the relaxation oscillation might be controlled by Von. The increasing current amplitudes could only quicken the oscillation velocity but not be able to eliminate it, which indicates that the relaxation oscillation might be an inherent behavior for the PCM cell.

Optimization of Anomalous Cells with High SET Resistance in Phase Change Memory Arrays

The resistance distribution in the crystalline (SET) state of phase change memory (PCM) is experimentally investigated at the array level using an 8 Mbit test chip. The SET distribution shows a high resistance tail, which potentially affects the reading margin of the chip. To further understand the anomalous behaviors of these tail cells, the SET resistances are characterized in terms of the programming pulse current magnitude and duration. These tail cells are probably caused by incomplete crystallization of the inactive region of phase change material. Finally, an optimization approach of applying a direct current of 0.6 mA to these tail cells is proposed and experimentally verified.

Circuit design for 128Mb PCRAM based on 40nm technology

In this paper, a 128Mb phase change random access memory based on phase change Ge2Sb2Te5 alloy has been designed in 40nm 4 metal level CMOS technology. Memory cell is the dual trench epitaxial pn junction diode. According to the feature of the 1D1R memory cell structure, array architecture and chip architecture have been optimized. The read access time is 30ns in simulation. The layout area is 6.6mm × 3.8mm.

The enhancement of write throughout for phase change memory

The unbalanced speed for writing 0 (Reset) and 1 (Set) of phase change memory (PCM) causes lots of internal timing fragmentation during conventional parallel writing process. This fragmentation is the bottleneck of PCM writing speed. In this work, a novel self-write method is developed to eliminate fragmentation and enhance write throughout. The experimental result shows that this method enhances write throughout by 10%–25%.

Automatic Switching System of Voltage Pulse and Current Pulse Test in Phase Change Memory Devices

Voltage pulse and current pulse test of phase change memory (PCM) device is realized by computer controlling pulse generator, digital source meter, current pulse generating circuit, switching circuit and other hardware devices. The PCM device test includes several modules of the relationship between current and voltage, voltage and current, resistance and voltage pulse width or height, resistance and current pulse width or height, and fatigue characteristics. In these test modules, the automatic switching system achieves the automatic switching between voltage pulse and current pulse test. The automatic switching system of voltage pulse and current pulse test can not only achieve the automation of engineering testing, but also can reduce the noise interference.

Investigation of data retention under current bias for phase change memory

With Phase-change memory (PCM), information can be stored as different resistance states even when not powered. In order to accurately characterize the reliability of PCM devices, data retention has to be tested carefully. In this paper, a new test method is applied to measure the data retention of T-shaped PCM devices. This method makes it possible to accelerate crystallization in the amorphous area by using current bias. The new method works based on the field-induced crystallization theory, and could be able to gather fast and detailed information about high-resistance state’s failure process, and at the same time, it could avoid issues related to high temperature. Experimental data for T-shaped PCM devices based on Ge2Sb2Te5 are presented and analyzed. An exponential trend-line of failure time t versus reciprocal bias current 1/I shows only negligible deviation of the measured data points, enabling the extrapolation of the retention behavior for ten-year lifetime. A maximum disturb current value of 5.08 μA is extracted to guarantee the ten years data retention requirement for PCM applications.

Comprehensive analysis and optimization of interface in device

The interface which should correspond to Ohmic contact between the TiN bottom electrode and the TiN adhesive layer is investigated. However, from the measured V-I curve, a non-linear relationship is observed. The previous research and the replotted V-I curve using double-logarithmic scale demonstrate that an oxide layer at the interface is the major reason for the non-linear relationship and that the conduction mechanism here follows the Space-Charge-Limited- Current mechanism. To eliminate the interface effect, a pulse current with a compliance is introduced. A phenomenon is observed that negative resistance occurs because of the capture of filament in the oxide layer. As the width of pulse current increases, the interface effect is eliminated due to the formation of a permanent conducting filament. And , the VI curve shows a linear relationship, representing that the interface corresponds to Ohmic contact and the interface effect has been eliminated efficiently.