Howard Thomas Olnowich

ALLNODE barrier synchronization network

This paper presents a proposed hardware solution using an existing multi-stage switching network for synchronizing N multiple processors at predetermined programmable barriers. The technique permits all N processors to access the network simultaneously and to perform synchronization in parallel using only several network cycles. The synchronization requires no additional network facilities, and consumes usually less than 5% of the bandwidth when merged onto the same multi-stage network that handles normal message traffic. The approach permits up to 2048 barriers, but can be expanded. The network is based on the Allnode Switch and Network concepts, a circuit-switching implementation, that permits a special barrier synchronization mode where all N processors are simultaneously attached to the network and can interact as if they were attached to a multi-drop bus.<<ETX>>

ALLNODE-RT: a real time, fault tolerant network

This paper presents a proposed multi-stage switching network for real-time systems which features: priority scheduling scalability, high bandwidth, low latency, fault tolerance, and breaking of lower priority connections. The fault-tolerant approach presented gives continuous availability in the presence of many failures, and the correction time is so rapid that real-time messages can be delivered before their deadlines expire. This is possible because the ALLNODE-RT Network contains numerous alternate paths between any two nodes. The ALLNODE-RT hardware searches for an available, non-failed path and guarantees the meeting of a deadline by dynamically increasing priority as the deadline approaches and breaking lower priority connections. The network is based on the existing ALLNODE Switch concept. The modifications required to evolve to a real-time switch are described, as well as the fault tolerance concepts.<<ETX>>