Robert Francis Lusch

Innovative techniques for improved testability

Three independent topics which illustrate innovative methods for improving testability are described. A technique which utilizes a card logic tester as a vehicle for evaluating the effectiveness of new chip-level tests is described. This technique allows rapid implementation and verification of various test algorithms as clip failure mechanisms are discovered. A methodology which combines simulation data with the capabilities of a tester language to provide early verification of the AC characteristics of components is presented. The authors consider tester language limitations and how adjustments can be made to component timing specifications to overcome these restrictions. These techniques were successfully implemented using Programming Language for Testing (PLT). With these methods, the testability and hence the quality of IBM products were improved in a cost-effective manner.<<ETX>>

Techniques for improved testability in the IBM ES/9370 system

The authors discuss three techniques used in the IBM ES/9370 series of processors to improve the testability, and hence the quality levels, of card assemblies. First they investigate the testing requirements and challenges presented by a nonvolatile static RAM and how they were met. Then they introduce a method which uses flush-through logic to provide improved access to array components. Next, the authors discuss how a compare circuit can be used to reduce I/O (input/output) requirements when testing an array. These algorithms were successfully implemented using programming Language for Testing (PLT). Background information and a detailed methodology for each of the techniques are provided.<<ETX>>