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Hsiao-Shu Chao

TSMC

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Publication

Featured researches published by Hsiao-Shu Chao.

Archive | 2013

Parasitic Capacitance Extraction for FinFETs

Chia-Ming Ho; Ke-Ying Su; Hsiao-Shu Chao; Yi-Kan Cheng; Ze-Ming Wu; Hsien-Hsin Sean Lee

Archive | 2012

Method of generating a bias-adjusted layout design of a conductive feature and method of generating a simulation model of a predefined fabrication process

Chia-Ming Ho; Ke-Ying Su; Hsiao-Shu Chao; Yi-Kan Cheng

Archive | 2013

MULTI-PATTERNING METHOD

Chin-Chang Hsu; Ying-Yu Shen; Wen-Ju Yang; Hsiao-Shu Chao; Yi-Kan Cheng

Archive | 2012

Tool and method for eliminating multi-patterning conflicts

Hung Lung Lin; Chin-Chang Hsu; Ying-Yu Shen; Wen-Ju Yang; Hsiao-Shu Chao; Yi-Kan Cheng; Chin-Hsiung Hsu; Huang-Yu Chen; Yi-Chuin Tsai; Yuan-Te Hou; Chung-Hsing Wang

Archive | 2012

Mask-shift-aware rc extraction for double patterning design

Lee-Chung Lu; Yi-Kan Cheng; Hsiao-Shu Chao; Ke-Ying Su; Cheng-Hung Yeh; Dian-Hau Chen; Ru-Gun Liu; Wen-Chun Huang

Archive | 2010

Chip-Level ECO Shrink

Huang-Yu Chen; Ho Che Yu; Chung-Hsing Wang; Hsiao-Shu Chao; Yi-Kan Cheng; Lee-Chung Lu

Archive | 2011

DECOMPOSITION AND MARKING OF SEMICONDUCTOR DEVICE DESIGN LAYOUT IN DOUBLE PATTERNING LITHOGRAPHY

Chin-Chang Hsu; Wen-Ju Yang; Hsiao-Shu Chao; Yi-Kan Cheng; Lee-Chung Lu

Archive | 2014

RC corner solutions for double patterning technology

Ke-Ying Su; Hsiao-Shu Chao; Yi-Kan Cheng

Archive | 2014

Semiconductor device design method, system and computer-readable medium

Ching-Shun Yang; Ze-Ming Wu; Hsiao-Shu Chao; Yi-Kan Cheng

Archive | 2012

Methodology for analysis and fixing guidance of pre-coloring layout

Chin-Chang Hsu; HungLung Lin; Wen-Ju Yang; Hsiao-Shu Chao; Yi-Kan Cheng

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Collaboration

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Yi-Kan Cheng

TSMC

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Ke-Ying Su

TSMC

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Lee-Chung Lu

TSMC

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Chin-Chang Hsu

TSMC

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Chung-Hsing Wang

TSMC

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Wen-Ju Yang

TSMC

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Chia-Ming Ho

TSMC

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Ho Che Yu

TSMC

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Chen-fu “Alex” Huang

TSMC

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Chih Sheng Tsai

TSMC

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