Lee-Chung Lu

Transistor-and Circuit-Design Optimization for Low-Power CMOS

CMOS-technology scaling has moved to a power-constrained condition regardless of the application segments. Power management in advanced CMOS technology drives the need to conciliate scaling-driven fundamental material limitations with product and application evolution requirements. Flexible CMOS technologies and tighter interaction between process development and circuit/system design are needed to efficiently realize systems on a chip. This paper reviews issues associated with transistor scaling and co-optimization for power-management circuit-design schemes for active-and leakage-power control. This paper also addresses the derived trends and implications on I/O and analog-transistor scaling.

Enhanced tunneling characteristics of PECVD silicon-rich-oxide (SRO) for the application in low voltage flash EEPROM

High tunneling efficiency is indispensable for the application of low voltage flash EEPROM. In this study the enhanced tunneling characteristics of the thin silicon-rich-oxide (SRO) films deposited using Plasma Enhanced Chemical Vapor Deposition (PECVD) as a tunneling injector was first reported. By optimizing the reactant gas ratios of [N/sub 2/O]/[SiH/sub 4/ during SRO deposition, the tunneling voltage of flash EEPROM can be 1/3 lower than that without PECVD SRO films. The significant tunneling efficiency is found to be caused by the micro Si-islands in SRO films. Micro Si-islands in SRO films enhance the electrical field of the tunneling oxide in flash EEPROM. A modified WKB tunneling approximation has been successfully applied to model the SRO tunneling characteristics. The field enhancement factor of SRO is also found to depend on the oxide electrical field, and is proportion to the inverse of oxide electrical field.