Hsien Chung

In Situ Stress and Reliability Monitoring on Plastic Packaging Through Piezoresistive Stress Sensor

Because of the coefficient of thermal expansion and the hygroscopic swelling mismatches on plastic packaging materials, stress and reliability issues on microelectronic packaging structures are extremely important for the packaging industry. Through the self-design test chips with the piezoresistive microstress sensors, this paper presents the experimental methodologies for stress and reliability monitoring on typical plastic ball-grid-array packaging. To this end, coefficients of the sensors are first calibrated, and stress monitoring is next performed with simultaneously thermal and hygroscopic loadings under steady-state and cyclic environments, respectively. The Weibull reliability model is next applied based on the experimental data and the parameters of the model are extracted. After real-time monitoring on stress variations during the reliability test, about 0.8 MPa of stress decrease is measured on each reliability cycle.

The advanced pattern designs with electrical test methodologies on through silicon via for CMOS image sensor

The through silicon via (TSV) technology brings a key to 3D integration on wafer level packaging (WLP) by stacking chips to generate direct electrical interconnecting paths. Most of the related literatures employed the daisy chain test patterns to measure the electrical continuity and to evaluate the single via resistance. However, the single via resistance is actually the contact resistance between the two metal layers at the via bottom. In this paper, we developed new test patterns with suitable electrical measurement methodologies to evaluate several typical performance, including the contact resistance, on TSV with better accuracy.

A complete resistance extraction methodology and circuit models for typical TSV structures

Through-silicon via (TSV) is one of the key technologies on three-dimensional integration packaging. In this article, an experimental methodology with circuit models was proposed for electrical characteristic tests on typical TSV structures. To this end, self-developed test patterns such as the via chains, the snake interconnections and the Kelvin structures with different dimensions were designed and manufactured. Suitable electrical measurement methodologies were next employed to characterise the element behaviours of the patterns. Based on the experimental data, electrical circuit models for the TSV structures were introduced and the parameters of the model were exacted. The validity and accuracy of the electrical model were finally verified and the TSV characteristic measurements can be performed through a simpler process.

In Situ Chip Stress Extractions for LFBGA Packages Through Piezoresistive Sensors

Piezoresistive sensors have been demonstrated to be an accurate and efficient tool for stress measurements on chip surfaces inside microelectronic packaging. In this work, test chips with piezoresistive stress sensors, diode temperature sensors as well as heaters were first designed, fabricated, and calibrated. We next packaged the test chips into low profile, fine pitch ball grid array (LFBGA) packaging with 196 balls and measured the stresses on chip surfaces inside the packaging. After measuring the packaging induced stress as well as the stress under stable environmental temperature rises, it was found that compressive stresses were obtained at room temperature, and the stresses were relaxed as temperature went up at a rate between 0.45 MPa/ °C and 0.60 MPa/ °C. For thermo-stress experiments, the temperatures on chip surfaces at different power levels were measured, and compressive chip stresses were first extracted. As the chip power increased, the compressive stresses became tensions. Since the LFBGA structure is thinner with higher packaging efficiency different results from our earlier plastic quad flat package stress measurements were observed and discussed. In addition, the final comparisons between the experimental data and the finite element simulations show good consistency.

Parameter Calibrations on MOSFET Stress Sensors

Due to the carrier mobility changes with the mechanical loading and its small size, the MOSFET ( m etal-oxi d e-semiconductor fi el d- e ffective-transistor) has the potential to be a suitable chip stress monitoring tool for microelectronic packaging. In this work, a complete and accurate approach to calibrate the coefficients for both types of MOSFET stress sensors under thermal and mechanical loadings was investigated quantitatively. Through data from different measurement modes on different types of MOSFET, the optimal experimental methodology was next proposed for the sensor applications on packaging stress extraction. The thermomechanical coupling coefficients for the selected experimental mode were finally extracted so that packaging stress measurements with MOSFET under elevated temperature can be performed more accurately.

Calibrate MOSFET Micro-Stress Sensors for Electronic Packaging

Stress measurements in microelectronic packaging through the MOSFET devices have attracted great attentions because the measurement is in-situ and nondestructive. In this study, a new assembled methodology was designed and applied so that the calibration procedures on MOSFET stress sensors can be simpler and more accurate. Under mechanical, thermal, and thermo-mechanical coupling effects, parameters of the MOSFET devices were extracted based on linear relationships between drain current variation and the mechanical and/or thermal effects, and the results suggested that the MOSFET devices is a useful in-situ stress sensorsin electronic packaging. It is concluded that the newly experimental design and the extracted parameters are useful for MOSFET stress sensors design and applications.

On the study of MOSFET micro-sensors for electronic packaging

The purpose of this paper is to study the MOSFET stress sensor behaviors and to develop the related measurement methodology. With the newly developed technology, the piezoresistance coefficients of the MOSFET were extracted, and the strain and temperature effect induced MOSFET characteristics were obtained. The results of this study can be used to adjust the chip structure in a packaging so that the optimal packaging technology and material can be chosen, and accuracies of the numerical analysis can be verified through experimental data with the new technology studied in this paper.

Stress coefficient extractions on MOSFET micro-sensors

The MOSFET (Metal-Oxide-Semiconductor Field-Effective-Transistor) has the potential to be a suitable chip stress monitoring tool for microelectronic packaging because the measurements are nondestructive, in-situ, real-time, and the sensor is relatively small. To this end, this paper studies the stress behaviors of both types of the MOSFET micro stress sensors. In this work, a self-developed four-point bending (4PB) measurement methodology is employed and the stress coefficient calibrations on the MOSFET sensors were next performed. After measurements, stress coefficients for both types of the MOSFET were successfully extracted with discussions. After comparing with the previous extracted temperature coefficients on the same devices, it is also concluded that the temperature effect is extremely important for the MOSFET sensor applications.

In-situ reliability monitoring on PBGA packaging through piezoresistive stress sensor

It is well known that the CTE mismatch and the hygroscopic swelling mismatch in a plastic packaging lead reliability issues so that a suitable extraction methodology on packaging stress and failure parameters are needed. To this end, we first designed and made the piezoresistive stress sensors for packaging stress measurements and performed the sensor calibrations. Test chips were next packaged into a typical plastic packaging and the hygroscopic stress were measured. Finally, a reliability test was performed to extract the long-term effects and the reliability parameters. It is concluded from the works that the hygroscopic mismatch stress is about 50 MPa and it is significant for the packaging. It is also concluded that the Weibull reliability model is suitable for the PBGA packaging, and the Weibull parameters were successfully extracted.

Parameter extractions and a new calibration methodology for MOSFET sensors

In this work, we studied the availability of p-type MOSFET with 1 mum channel width and 0.15 mum channel length as a stress sensor. Under mechanical, thermal, and thermo-mechanical coupling effects, parameters of the MOSFET devices were extracted based on a new measurement methodology, and linear relationships between drain current variation and stress and/or thermal effects were obtained. According to the measurement data, the extremely important thermal effect was also noted. It is concluded in this work that the newly experimental design and the extracted parameters are useful for MOSFET stress sensors design and applications.