Ben-Je Lwo

Calibrate Piezoresistive Stress Sensors Through the Assembled Structure

In this work, a simple assembled structure was designed and fabricated so that the calibration procedures on piezoresisitve stress sensors for microelectronic packaging can be simpler, more accurate, and more efficient. After comparing with the previous work results, validity of the aforementioned new structure was next demonstrated through experimental data. Since many accessory experimental facilities employed in traditional calibration procedure become unnecessary, the new methodology takes great advantage on piezoresisitve coefficient calibrations, especially for calibration at temperature other than room temperature.

In Situ Stress and Reliability Monitoring on Plastic Packaging Through Piezoresistive Stress Sensor

Because of the coefficient of thermal expansion and the hygroscopic swelling mismatches on plastic packaging materials, stress and reliability issues on microelectronic packaging structures are extremely important for the packaging industry. Through the self-design test chips with the piezoresistive microstress sensors, this paper presents the experimental methodologies for stress and reliability monitoring on typical plastic ball-grid-array packaging. To this end, coefficients of the sensors are first calibrated, and stress monitoring is next performed with simultaneously thermal and hygroscopic loadings under steady-state and cyclic environments, respectively. The Weibull reliability model is next applied based on the experimental data and the parameters of the model are extracted. After real-time monitoring on stress variations during the reliability test, about 0.8 MPa of stress decrease is measured on each reliability cycle.

Measurement of Moisture-Induced Packaging Stress With Piezoresistive Sensors

Moisture is one of the major contributing factors in fracture and reliability issues for microelectronic packaging. To characterize the moisture-induced stress distribution inside the packaging structure, an in situ, quantitative, and nondestructive experimental methodology is needed. This paper proposes the use of piezoresistive sensors to measure moisture-induced stress in a plastic low profile, fine pitch, ball grid array (LFBGA) packaging. The measurements include hygroscopic swelling stress extractions and real-time stress monitoring of the popcorn phenomenon, and the results associated with gravimetric analyses are reported. Postreflow scanning acoustic microscope (SAM) inspection results and cross section observations are used as experimental verification. Comparing with thermal stresses previously measured on the same package, it is found that the hygroscopic mismatch stress is significant and important for package engineers. In addition, piezoresistive sensors were proven useful in this work for recording popcorn occurrence and monitoring the stress drops at the popcorn initiation.

The advanced pattern designs with electrical test methodologies on through silicon via for CMOS image sensor

The through silicon via (TSV) technology brings a key to 3D integration on wafer level packaging (WLP) by stacking chips to generate direct electrical interconnecting paths. Most of the related literatures employed the daisy chain test patterns to measure the electrical continuity and to evaluate the single via resistance. However, the single via resistance is actually the contact resistance between the two metal layers at the via bottom. In this paper, we developed new test patterns with suitable electrical measurement methodologies to evaluate several typical performance, including the contact resistance, on TSV with better accuracy.

A complete resistance extraction methodology and circuit models for typical TSV structures

Through-silicon via (TSV) is one of the key technologies on three-dimensional integration packaging. In this article, an experimental methodology with circuit models was proposed for electrical characteristic tests on typical TSV structures. To this end, self-developed test patterns such as the via chains, the snake interconnections and the Kelvin structures with different dimensions were designed and manufactured. Suitable electrical measurement methodologies were next employed to characterise the element behaviours of the patterns. Based on the experimental data, electrical circuit models for the TSV structures were introduced and the parameters of the model were exacted. The validity and accuracy of the electrical model were finally verified and the TSV characteristic measurements can be performed through a simpler process.

Reliability analyses on a TSV structure for CMOS image sensor

In order to assess the reliability behavior of a typical TSV structure, this study describes the reliability tests to qualify the samples with three types of the TSV test-keys, which includes the Kelvin structure, the via-chain, and the meander metal lines. With enough number of the samples for statistic analyses, resistances of the samples were first found increased after the preconditioning process. The temperature cycling tests (TCT) and the temperature humidity cycling tests (THTC) were next performed according to the JEDEC standards, and resistances variations on the samples were recorded during the tests. The Weibull parameters for the testing samples were finally extracted from the testing data to obtain the lifetime performance of the samples.

In Situ Chip Stress Extractions for LFBGA Packages Through Piezoresistive Sensors

Piezoresistive sensors have been demonstrated to be an accurate and efficient tool for stress measurements on chip surfaces inside microelectronic packaging. In this work, test chips with piezoresistive stress sensors, diode temperature sensors as well as heaters were first designed, fabricated, and calibrated. We next packaged the test chips into low profile, fine pitch ball grid array (LFBGA) packaging with 196 balls and measured the stresses on chip surfaces inside the packaging. After measuring the packaging induced stress as well as the stress under stable environmental temperature rises, it was found that compressive stresses were obtained at room temperature, and the stresses were relaxed as temperature went up at a rate between 0.45 MPa/ °C and 0.60 MPa/ °C. For thermo-stress experiments, the temperatures on chip surfaces at different power levels were measured, and compressive chip stresses were first extracted. As the chip power increased, the compressive stresses became tensions. Since the LFBGA structure is thinner with higher packaging efficiency different results from our earlier plastic quad flat package stress measurements were observed and discussed. In addition, the final comparisons between the experimental data and the finite element simulations show good consistency.

Thermal simulation on typical high power diode packaging

With the assistances from iteration methodology for heat dissipation property analyses and the effective material properties for the relatively complex PCB structures, this paper extracts the thermal resistance and the transient thermo-mechanical behaviors during reflow for two compactable high power diode packaging through the ANSYS software. After the simulations, further improvements on packaging structure designs were discussed according to the temperature and stress results.

A multifunctional test chip for microelectronic packaging and its application on RF property measurements

In this paper, we developed a multifunctional test chip for property extractions on packaging design. Components in this test chip include diodes as the temperature sensor; polysilicon units as the heater; piezoresistors as the stress sensor; and pads as well as the related metal connector designs for electrical parameter extractions. To save sensor numbers and connecting wires, sensors on the test chip surface were put according to structure symmetry. Since different microelectronic packaging has individual size, components on test chip surface were laid based on assembly of small unit cells so that the flexible test chip size can be employed to fit requirements from different packaging dimensions. Besides, we considered the inductance/capacitance extractions of packages for high frequency condition. A test structure was finally designed to cooperate the QFP packages for the RLC measurement, and the availability of the designed was demonstrated from testing data.

LFBGA packaging stress measurements with piezoresistive sensors

Piezoresistive sensor has been demonstrated to be an accurate and efficient tool for stress measurements on chip surfaces inside microelectronic packaging. In this work, square test chips with four piezoresistive stress sensors and the accompanied diode temperature sensors have been first designed, fabricated and calibrated. A heater was also laid at the chip center. We next packaged test chips into 196-ball LFBGA (Low profile, Fine pitch BGA) packaging and measured stresses on chip surfaces inside the packaging. After measuring the packaging-induced stresses as well as stresses under constant environment temperatures, it was found that compressive stresses were obtained at room temperature, and the compressive stresses are relaxed as temperature increases. It was also found in the same experiments that the average slopes of the temperature-stress curves are between 0.45 Mpa//spl deg/C/spl sim/0.65 Mpa//spl deg/C, and localized stress distributions are observed. For thermal stress experiments, temperatures on chip surfaces at different power levels were first derived. Compressive chip stresses were next measured and the stresses then become tension as the chip power increased. Since all of the measured stresses are much less than the yielding stress, it is concluded that chips inside 196-ball LFBGA packaging will not failure due to thermomechanical effects during regular operations.