Hsing-Jen Wann

A capacitorless DRAM cell on SOI substrate

We propose a capacitorless DRAM (CDRAM) cell on SOI substrate with large READ current (>100 /spl mu/Aspl mu/m), small cell size, and simple fabrication process. PISCES simulations are used to analyze the memory cell operations. The CDRAM cell size is that of a transistor, which makes it very attractive for high density memory applications. Since the fabrication process of CDRAM is compatible with that of the general purpose SOI CMOS and complementary BiCMOS process, CDRAM can also be used for integrated on-chip memory and is an interesting candidate as the technology driver of SOI VLSI.<<ETX>>

Design for suppression of gate-induced drain leakage in LDD MOSFETs using a quasi-two-dimensional analytical model

A systematic study of gate-induced drain leakage (GIDL) in single-diffusion drain (SD), lightly doped drain (LDD), and fully gate-overlapped LDD (GOLD) NMOSFETs is described. Design curves quantifying the GIDL dependence on gate oxide thickness, phosphorus dose, and spacer length are presented. In addition, a new, quasi-2-D analytical model is developed for the electric field in the gate-to-drain overlap region. This model successfully explains the observed GIDL dependence on the lateral doping profile of the drain. Also, a technique is proposed for extracting this lateral doping profile using the measured dependence of GIDL current on the applied substrate bias. Finally, the GIDL current is found to be much smaller in lightly doped LDD devices than in SD or fully overlapped LDD devices, due to smaller vertical and lateral electric fields. However, as the phosphorus dose approaches 10/sup 14//cm/sup 2/, the LDD and fully overlapped LDD devices exhibit similar GIDL current. >

High-endurance ultra-thin tunnel oxide in MONOS device structure for dynamic memory application

Ultra-thin tunnel oxide can conduct very high current through oxide via direct tunneling, and charge-to-breakdown increases dramatically due to less oxide damage. These facts point to a possibility of using thin tunnel oxide in the floating-gate device structure for dynamic memory applications. We have chosen MONOS structure in this study due to its immunity to pinhole-induced leakage and back-tunneling. The memory device exhibits fast WRITE/ERASE speed, high-endurance, long data retention and non-destructive READ. Further improvements are expected through process optimization.<<ETX>>

The impact of device scaling and power supply change on CMOS gate performance

Based a new empirical mobility model that is solely dependent on V/sub gs/, V/sub t/, and T/sub ox/ and a corresponding saturation drain current (I/sub dsat/) model, the impact of device scaling and power supply voltage change on CMOS inverters performance is investigated in this paper. It shows that the T/sub ox/ which maximizes inverters speed may be thicker than reliability consideration requires. In addition, very high speed can be achieved even at low V/sub dd/ (for low power applications) if V/sub t/ can be lowered.

Effects of N/sub 2/O anneal and reoxidation on thermal oxide characteristics

The effects of post-oxidation N/sub 2/O anneal on conventional thermal oxide are studied. The oxide thickness increase resulting from N/sub 2/O anneal is found to be self-limiting and insensitive to initial oxide thickness, which makes the thickness of the resulting oxide easy to control. The N/sub 2/O anneal leads to increased resistance against injection-induced interface-state generation and to reduced hole trapping. No further quality improvement is found when the N/sub 2/O-annealed oxide is subject to an additional reoxidation. This finding confirms that nitrogen incorporation in the absence of hydrogen is responsible for improving the quality of the conventional oxides.<<ETX>>

Interface characterization of fully-depleted SOI MOSFET by a subthreshold I-V method

Interface state densities can dramatically affect the performances of MOSFETs by causing threshold voltage shift and mobility degradation. In SOI structures, due to the complex multi-interface nature and small gate area, the interface state characterization still remains a very challenging problem. Conventional C-V method is not suitable for investigating interfaces in SOI MOS devices, mainly because of the large area needed and the high series resistance in thin-film. Several other measurement techniques based on currents rather than capacitance have been proposed. In this work, an evolved technique for characterizing interface state density in fully-depleted SOI MOSFETs is presented. By measuring subthreshold swing of the SOI MOSFETs, the interface state density can be determined. The distribution of both front- and back-interface state densities in the bandgap can be evaluated by applying a rigorous one-dimensional analytical model for FD-SOI MOSFETs operating in the weak inversion regime. In addition, this technique has been applied successfully to the comparison of interface qualities of various SOI wafers and the study of electrical stress effect. The SOI devices used in this study were n-channel and p-channel MOSFETs fabricated with submicron CMOS technology on both SIMOX and Bonded-and-Etchback SOI (BESOI) wafers.

Improvement of charge trapping characteristics of N/sub 2/O-annealed and reoxidized N/sub 2/O-annealed thin oxides

It is found that increasing N/sub 2/O annealing temperature and time monotonically reduces electron trapping in the resulting oxides. The improvement increases with oxide thickness. Reoxidation does not enhance but reduces the improvement. The behavior is different from and simpler to understand than that after NH/sub 3/ annealing, apparently due to the absence of deleterious hydrogen. Hole trapping and interface trap generation are also suppressed by N/sub 2/O annealing, though an optimum anneal condition may exist. Charge to breakdown exhibits modest improvement consistent with reduced electron trapping.<<ETX>>

An accurate semi-empirical saturation drain current model for LDD n-MOSFET

Based on a new empirical mobility model which is solely dependent on V/sub gs/, V/sub t/ and T/sub ox/, a corresponding semiempirical I/sub dsat/ model for n-MOSFET including velocity saturation, mobility degradation due to increased vertical effective field, and source/drain series resistance of LDD structures is reported in this paper. A good agreement among the model and the measurement data from several different technologies is shown. Prediction of I/sub dsat/ for the future generations of device scaling and low-power applications by using this new model is presented.

Gate-induced band-to-band tunneling leakage current in LDD MOSFETs

Theoretical and experimental studies are presented to model the gate-induced drain leakage(GIDL) current due to band-to-band tunneling, which is one of the major leakage components in off-state MOSFETs. The model shows a good agreement with the experimental data for more than 7 decades of current magnitudes. Therefore the impact of this tunneling leakage current can be correctly evaluated. Based on this model, the impact of GIDL on low off-state leakage drain engineering and on oxide scaling is investigated.<<ETX>>

Channel doping engineering of MOSFET with adaptable threshold voltage using body effect for low voltage and low power applications

With the scaling of the power supply voltage V/sub DD/ in low voltage and low power VLSI, the threshold voltage of the MOSFET device needs to be reduced to retain the device performance in terms of current driving capability and switching speed. Recently MOSFET devices whose threshold voltages can be adapted during the transistor operation using the body effect have been proposed for low voltage and low power VLSI applications. In these devices, the threshold voltages are reduced by forward-biasing the body-to-source junction. In this paper we study the effect of the channel doping engineering on this threshold voltage reduction scheme.