Hsiu-Ming Chang

Test cost reduction through performance prediction using virtual probe

The virtual probe (VP) technique, based on recent breakthroughs in compressed sensing, has demonstrated its ability for accurate prediction of spatial variations from a small set of measurement data. In this paper, we explore its application to cost reduction of production testing. For a number of test items, the measurement data from a small subset of chips can be used to accurately predict the performance of other chips on the same wafer without explicit measurement. Depending on their statistical characteristics, test items can be classified into three categories: highly predictable, predictable, and un-predictable. A case study of an industrial RF radio transceiver with more than 50 production test items shows that a good fraction of these test items (39 out of 51 items) are predictable or highly predictable. In this example, the 3σ error of VP prediction is less than 12% for predictable or highly predictable test items. Applying the VP technique can on average replace 59% of test measurement by prediction and, consequently, reduce the overall test time by 57.6%.

Digitally-Assisted Analog/RF Testing for Mixed-Signal SoCs

We propose a testing methodology for analog and radio-frequency (RF) circuitry that incorporates digital circuits for performance calibration and adaptation. We explore the reuse of built-in digital calibration circuitry, along with minor digital design-for-testability (DfT) modifications, to test and characterize analog/RF circuit performance. By observing the digital tuning signals captured in the digital calibration circuitry, the analog/RF performance can be closely estimated, thus enabling cost-effective Go/No-Go production testing. In this paper, we illustrate this testing methodology using a case study of a digitally-calibrated Weaver image-reject receiver.

Recent Advances in Analog, Mixed-Signal, and RF Testing

Due to the lack of widely applicable fault models, testing for analog, mixed-signal (AMS), and radio frequency (RF) circuits has been, and will continue to be, primarily based on checking their conformance to the specifications. However, with the higher level of integration and increased diversity of specifications for measurement, specification-based testing is becoming increasingly difficult and costly. As a result, design for testability (DfT), combined with automatic test stimuli generation, has gradually become a necessity to ensure test quality at an affordable cost. This paper provides an overview of cost-effective test techniques that either enhance circuit testability, or enable built-in self-test (BIST) for integrated AMS/RF frontends. In addition, we introduce several low-cost testing paradigms including the loopback testing, alternate testing, and digitally-assisted testing that offer the promise of significant test cost reduction with little or even no compromise in test quality. Moving forward, in addition to screening the defective parts, testing will play an increasingly important role in supporting other post-silicon quality assurance functions such as post-silicon validation, tuning, and in-field reliability of system chips.

Calibration and Testing Time Reduction Techniques for a Digitally-Calibrated Pipelined ADC

Modern mixed-signal/RF circuits with digital calibration capabilities could achieve significant performance improvements once the calibration process is completed; however, the calibration time is often very long – in the order of hundreds of milliseconds or even seconds. As testing such devices would require completion of calibration first, lengthy calibration time would result in unacceptably long testing time. In this paper, we propose design-for-testability modifications and acceleration techniques for adaption algorithms to reduce the calibration time required for testing a digitally-calibrated pipelined ADC. For the pipelined ADC proposed in [2], simulation results show that the proposed techniques can achieve a 60X reduction in the calibration time.

A Built-in self-calibration scheme for pipelined ADCs

There is a strong demand for both calibrating and testing the ADC performance before and after packaging for mixed-signal SoCs and SiPs. In this paper, we propose a built-in self-calibration scheme that offers digitally-controlled calibration of a pipelined ADC without using external stimulus. We further propose a self-testing strategy that uses the effective number of bits (ENOB) derived directly from the steady-state error of the self-calibration process for go/no-go testing as well as for performance binning. This testing process will not incur any additional test time beyond that required for calibration.

An error tolerance scheme for 3D CMOS imagers

A three-dimensional (3D) CMOS imager constructed by stacking a pixel array of backside illuminated sensors, an analog-to-digital converter (ADC) array, and an image signal processor (ISP) array using micro-bumps (ubumps) and through-silicon vias (TSVs) is promising for high throughput applications. However, due to the direct mapping from pixels to ISPs, the overall yield relies heavily on the correctness of the ubumps, ADCs and TSVs - a single defect leads to the information loss of a tile of pixels. This paper presents an error tolerance scheme for the 3D CMOS imager that can still deliver high quality images in the presence of μbump, ADC, and/or TSV failures. The error tolerance is achieved by properly interleaving the connections from pixels to ADCs so that the corrupted data, if any, can be recovered in the ISPs. A key design parameter, the interleaving stride, is decided by analyzing the employed error correction algorithm. Architectural simulation results demonstrate that the error tolerance scheme enhances the effective yield of an exemplar 3D imager from 46% to 99%.

A self-testing and calibration method for embedded successive approximation register ADC

This paper presents a self-testing and calibration method for the embedded successive approximation register (SAR) analog-to-digital converter (ADC). We first propose a low cost design-for-test (DfT) technique which tests a SAR ADC by characterizing its digital-to-analog converter (DAC) capacitor array. Utilizing DAC major carrier transition testing, the required analog measurement range is just 4 LSBs; this significantly lowers the test circuitry complexity. Then, we develop a fully-digital missing code calibration technique that utilizes the proposed testing scheme to collect the required calibration information. Simulation results are presented to validate the proposed technique.

Time-Multiplexed Online Checking

There is a growing demand for online hardware checking capability to cope with increasing in-field failures resulting from variability and reliability problems. While many online checking schemes have been proposed, their area overhead remains too high for cost-sensitive applications. In this paper, we introduce a Time-Multiplexed Online Checking (TMOC) scheme using embedded field-programmable blocks for checker implementation, which enables various system parts to be checked dynamically in-field in a time-multiplexed fashion. The test quality analyses using a probabilistic model show that TMOC could maintain high fault coverage that is similar to traditional dedicated checkers. We conducted a case study of an H.264 decoder design that demonstrates our TMOC scheme provides a significant reduction in chip area and power overhead for online checkers at the cost of increased fault detection latency. We have successfully implemented and demonstrated our proposed TMOC scheme using a single Field-Programmable Gate Array (FPGA) chip.

Calibration-assisted production testing for digitally-calibrated ADCs

This paper presents a production test strategy for digitally-calibrated analog-to-digital converters (ADCs) that incorporate an equalization-based calibration scheme. By analyzing the data obtained in calibration, devices that fail certain static or dynamic specifications can be identified without any additional testing time beyond calibration. The foundation of this test strategy for the ADCs lies on the strong correlations between calibration and functional testing so that devices which violate specifications can be identified by checking the range of steady-state fluctuation in the calibration data. We further develop calibration stimuli to maximize the failing symptoms for fault detection. Simulation results on a pipelined ADC shows that the proposed strategy can effectively pre-screen a good fraction of defective devices that fail static and dynamic specifications including the gain/offset errors and the effective-number of bits (ENOB).

Tester-Assisted Calibration and Screening for Digitally-Calibrated ADCs

This paper presents a low-cost production test strategy for digitally-calibrated analog-to-digital converters (ADCs) that incorporate an equalization-based background calibration scheme. The test time of these designs is dominated by the long calibration time required prior to conducting the final testing. To reduce overall test time, we present a two-step calibration approach that significantly reduces calibration time without compromising test coverage. In addition, by analyzing the data obtained in calibration, devices that fail certain static or dynamic specifications can be identified without incurring any additional test time beyond calibration, thereby enabling early rejection. To minimize calibration time and maximize failing symptoms for fault detection, we propose using specific calibration stimuli. Simulation results for a pipelined ADC shows that the proposed strategy reduces the total test time by 80%. This is achieved by reducing the calibration time, as well as by prescreening a good fraction of defective devices that fail static and dynamic specifications including the gain/offset errors and the effective number of bits (ENOB).