Jiun-Lang Huang

Power Supply Noise Reduction for At-Speed Scan Testing in Linear-Decompression Environment

Yield loss caused by excessive power supply noise has become a serious problem in at-speed scan testing. Although X-filling techniques are available to reduce the launch cycle switching activity, their performance may not be satisfactory in the linear-decompressor-based test compression environment. This paper solves this problem by proposing a novel integrated automatic test pattern generation scheme that efficiently and effectively performs compressible low-capture-power X -filling. Related theoretical principles are established, based on which the problem size is substantially reduced. The proposed scheme is validated by benchmark circuits, as well as an industry design in the embedded deterministic test environment.

A Built-In TFT Array Charge-Sensing Technique for System-on-Panel Displays

For modern display systems, thorough testing of the TFT array is a critical element in yield management. However, for system-on-panel displays which integrate drivers, timing units, and controllers on the same substrate (usually glass) as the TFT array, access to the array data and scan lines is complicated. To reduce the tester complexity, we propose a low area overhead and offset compensated charge sensing capable source driver design which facilitates built-in TFT array charge sensing. To reduce the number of test access ports, a serial voltage readout scheme is proposed. Simulation results using LTPS technology are shown to validate the proposed technique.

Synergistic Reliability and Yield Enhancement Techniques for Embedded SRAMs

Single isolated fault (SIF) stands for about 60%-70% of the total number of defects and is rather redundancy hungry since a spare row or a column is required for repairing each SIF. Therefore, manufacturing yield will decrease if we do not allocate sufficient spare resources. In this paper, instead of the traditional fault replacement techniques, synergistic techniques that integrate both fault replacement and fault masking techniques are proposed. With our approaches, SIFs are masked instead of the traditional replacement for repairing. For other minor fault types (e.g., faulty rows and faulty columns), the fault replacement technique is used as usual. According to simulation results, repair rates can be improved significantly. The proposed techniques can be integrated with the conventional built-in self-repair with nearly negligible hardware overhead.

An ADC/DAC loopback testing methodology by DAC output offsetting and scaling

This paper presents a loopback methodology for static linearity testing of an ADC/DAC pair; the key idea is to raise the effective ADC and DAC resolution by scaling the DAC output. First, during ADC testing, we scale down the DAC output to achieve the needed test stimulus resolution and adjust the DAC output offset to cover the ADC full-scale range. Then, for DAC testing, we raise the effective ADC resolution by scaling up the DAC output. Both simulation and measurement results are presented to validate the proposed technique.

A Low Communication Overhead and Load Balanced Parallel ATPG with Improved Static Fault Partition Method

This paper presents a parallel ATPG to speed up the test pattern gen- eration process. The ATPG adopts the master-slave architecture to reduce the inter-process communication. Also, a smart fault list broadcast and fault partition technique is proposed to reduce test pattern inflation. Simulation results show that close to linear speed-up can be achieved for up to 7 slave processes.

A circular pipeline processing based deterministic parallel test pattern generator

Parallel programming is an attractive solution to accelerate test pattern generation (TPG); however, the associated non-determinism often leads to non-reproducible test pattern sets. In this paper, the circular pipeline processing (CPP) principle is proposed to facilitate deterministic parallel TPG. CPP preserves the task processing orders that are necessary to ensure TPG determinism with low inter-thread synchronization overhead. Based on CPP, a deterministic parallel test pattern generator is developed; it guarantees to produce the same test pattern set regardless of the thread timing and the thread count. Experimental results on benchmark circuits show that the proposed test pattern generator exhibits close-to-linear speedup for at least up to 12 threads.

On Guaranteeing Capture Safety in At-Speed Scan Testing with Broadcast-Scan-Based Test Compression

Capture safety has become a major concern in at-speed scan testing since strong power supply noise caused by excessive launch switching activity (LSA) at transition launching in an at-speed test cycle often results in severe timing-failure-induced yield loss. Recently, a basic RM (rescue-&-mask) test generation scheme was proposed for guaranteeing capture safety rather than merely reducing LSA to some extent. This paper extends the basic RM scheme to broadcast-scan-based test compression by uniquely solving two test-compression-induced problems, namely (1) input X-bit insufficiency (i.e., fewer input X-bits are available for LSA reduction due to test compression) and (2) output X-bit impact (i.e., output X-bits may reduce fault coverage due to test response compaction). This leads to the broadcast-RM (broadcast-scan-based rescue-&-mask) test generation scheme. Evaluations on large benchmark circuits and an industrial circuit of about 1M gates clearly demonstrate that this novel scheme can indeed guarantee capture safety in at-speed scan testing with broadcast-scan-based test compression while minimizing its impact on both test quality and test costs.

An MCT-Based Bit-Weight Extraction Technique for Embedded SAR ADC Testing and Calibration

This paper presents a self-testing and calibration technique for the embedded successive approximation register (SAR) analog-to-digital converter (ADC) in system-on-chip (SoC) designs. We first proposed a low cost design-for-test (DfT) technique that estimates the SAR ADC performance before and after calibration by characterizing its digital-to-analog converter (DAC) capacitor weights (bit weights). Utilizing major carrier transition (MCT) testing, the required analog measurement range is only about 1 LSB; this significantly reduces test circuitry complexity. Then, we develop a fully-digital calibration technique that utilizes the extracted bit weights to correct the non-ideal I/O behavior induced by capacitor mismatch. Simulation results show that (1) the proposed testing technique achieves very high test accuracy even in the presence of large noise, and (2) the proposed calibration technique effectively improves both static and dynamic performances of the SAR ADC.

Testing and Calibration of SAR ADCs by MCT-Based Bit Weight Extraction

In this paper, a bit weight extraction technique is proposed to test and calibrate the successive approximation register (SAR) analog-to-digital converter (ADC). The proposed technique is based on major carrier transition (MCT) testing, the MCTs are generated through simple capacitor switching and then measured by the embedded comparator and a coarse design-for-test (DfT) digital-to-analog converter (DAC) that couples to the capacitor DAC (CDAC). From the results, the individual bit weights are extracted and the ADC performance can thus be estimated and calibrated. Simulation results show very high test accuracy and linearity improvement can be achieved by the proposed technique.

CSER: BISER-based concurrent soft-error resilience

This paper presents a concurrent soft-error resilience (CSER) scheme with features that aid manufacturing test, online debug, and defect tolerance. The proposed CSER scheme is based on the built-in soft-error resilience (BISER) technique [4]. A BISER cell is redesigned into various robust CSER cells that provide slow-speed snapshot, manufacturing test, slow-speed signature analysis, and defect tolerance capabilities. The cell-level area, power, and performance overhead of the robust CSER cells were found to be generally within 1% to 22% of the BISER cell.