Hsuan-Yu Liu

A 1-GS/s FFT/IFFT processor for UWB applications

In this paper, we present a novel 128-point FFT/IFFT processor for ultrawideband (UWB) systems. The proposed pipelined FFT architecture, called mixed-radix multipath delay feedback (MRMDF), can provide a higher throughput rate by using the multidata-path scheme. Furthermore, the hardware costs of memory and complex multipliers in MRMDF are only 38.9% and 44.8% of those in the known FFT processor by means of the delay feedback and the data scheduling approaches. The high-radix FFT algorithm is also realized in our processor to reduce the number of complex multiplications. A test chip for the UWB system has been designed and fabricated using 0.18-/spl mu/m single-poly and six-metal CMOS process with a core area of 1.76/spl times/1.76 mm/sup 2/, including an FFT/IFFT processor and a test module. The throughput rate of this fabricated FFT processor is up to 1 Gsample/s while it consumes 175 mW. Power dissipation is 77.6 mW when its throughput rate meets UWB standard in which the FFT throughput rate is 409.6 Msample/s.

A dynamic scaling FFT processor for DVB-T applications

This paper presents an 8192-point FFT processor for DVB-T systems, in which a three-step radix-8 FFT algorithm, a new dynamic scaling approach, and a novel matrix prefetch buffer are exploited. About 64 K bit memory space can be saved in the 8 K point FFT by the proposed dynamic scaling approach. Moreover, with data scheduling and pre-fetched buffering, single-port memory can be adopted without degrading throughput rate. A test chip for 8 K mode DVB-T system has been designed and fabricated using 0.18-/spl mu/m single-poly six-metal CMOS process with core area of 4.84 mm/sup 2/. Power dissipation is about 25.2 mW at 20 MHz.

A 480Mb/s LDPC-COFDM-based UWB baseband transceiver

A low-density parity-check (LDPC) coded OFDM-based UWB baseband transceiver features a semi-regular LDPC CODEC, a parallel pipelined FFT, and a division-free channel equalizer. The chip is implemented in a standard 0.18 /spl mu/m CMOS process and achieves a 480Mbit/s data rate with an energy consumption of 1.2nJ/b.

A 1.8V 250mW COFDM baseband receiver for DVB-T/H applications

A DVB-T/H baseband receiver with multi-stage power control, 2D linear channel equalizer, synchronizer, 2/4/8k-point FFT, and Viterbi/RS decoder is implemented in 0.18mum CMOS. At the highest data rate of 31.67Mb/s, it overcomes 70Hz Doppler frequency and consumes 250mW with a die size of 6.9 times 5.8mm2

A 31.2mW UWB Baseband Transceiver with All-Digital I/Q-Mismatch Calibration and Dynamic Sampling

A MB-OFDM UWB baseband transceiver with I/Q-mismatch (IQM) calibration and dynamic sampling (DS) is presented. It calibrates IQM by 2dB gain and 20 degree phase errors, releasing IQM tolerance to 10times of existing designs. The DS reduces ADC sampling rate to 1/9 ~ frac12 of existing designs, resulting in at least 43% ADC power saving. Measured power consumes 31.2mW at 480Mb/s data rate

An area and power efficient frame synchronizer for 480Mb/s OFDM-based UWB system

A frame synchronizer is proposed for OFDM-based UWB system. Integrating the improved matched filters and dynamic threshold design, the proposed design can reduce 65% area and 58% power with an acceptable performance loss. It can achieve 528MS/s throughput for 480Mb/s UWB system in 0.18/spl mu/m CMOS process.

A joint scheme of decision-directed channel estimation and weighted-average phase error tracking for OFDM WLAN systems

In this paper, a joint scheme of decision-directed channel estimation (DDCE) and weighted-average phase error tracking (WAPET) for OFDM WLAN systems is presented. With algorithm exploration, the proposed joint scheme makes synchronization more robust to overcome time-variant multipath fading, carrier frequency offset, and sampling clock offset. In CE accuracy measurement, the proposed joint scheme achieves better 8~20 dB gain in estimation mean-square-error compared with conventional approaches. In system simulation, the proposed scheme contributes 2.15~2.3 dB gain in SNR for 10% packet error rate (PER) demanded by IEEE 802.11a in 6 Mbits/s~54 Mbits/s transmission modes

A MLP/BP-based equalizer for NRZ signal recovery in band-limited channels

A multi-layered perceptron neural network with the backpropagation algorithm (MLP/BP) is realized as an equalizer for nonreturn-to-zero (NRZ) signal recovery in band-limited channels. It is applied as an adaptive filter to recover the NRZ signal. By computer simulations, the proposed design can recover 100 MHz NRZ data in a 10 MHz channel.

Combining adaptive smoothing and decision-directed channel estimation schemes for OFDM WLAN systems

In this paper, a new channel estimation method for OFDM WLAN systems is proposed. This proposal mainly consists of smoothing filtering and decision-directed tracking loop schemes, where the former is used to enhance performance at low SNR and the latter is exploited to enhance performance at high SNR respectively. Together with an adaptive channel management, better performance in terms of MSE and PER can be achieved. Simulation shows the proposed method (1) achieves better 9.0dB /spl sim/ 13.0dB gain in MSE than zero forcing criterion and better 2.0dB gain in MSE than conventional approaches in BPSK transmission, and (2) contributes 0.8dB /spl sim/ 2.0dB gain in SNR for 10% PER in different transmission modes.

A 528MS/s frequency synchronizer for OFDM-based UWB system

A novel frequency synchronizer is proposed for 528MHz OFDM-based UWB system. It can reduce 75% memory and 59% power consumption through a low-power scheme based on data partition. Measured result shows the proposed design can achieve 528MSamples/s throughput in 0.18/spl mu/m CMOS process.