Terng-Yin Hsu

An all-digital phase-locked loop (ADPLL)-based clock recovery circuit

A new algorithm for all-digital phase-locked loops (ADPLL) with fast acquisition and large pulling range is presented in this paper. Based on the proposed algorithm, portable cell-based implementations for clock recovery with functions of a frequency synthesizer and on-chip clock generator are completed by standard cell. These modules have been designed and verified on a 0.6-/spl mu/m CMOS process. Test results are summarized as follows: 1) the proposed ADPLL can satisfy full locked bandwidth and fast acquisition within one data transition; 2) the on-chip clock generator can generate any target clock rate f/sub clock/; and 3) the function of nonreturn-to-zero clock recovery has a maximum f/sub clock//4 recovering capability with a locking range of (/spl tau//sub input//spl plusmn//spl tau//sub input//2)) where /spl tau//sub input/ is the input period.

A novel technique for I/Q imbalance and CFO compensation in OFDM systems

In this paper, a novel baseband IQ estimation and compensation technique is proposed to overcome the joint effects of CFO (carrier frequency offset) and IQ imbalance. The proposed method uses a one-shot algorithm which is able to estimate and compensate the non-ideal effect up to a gain error of 1 dB, phase error of 10/spl deg/, and CFO of 50 ppm at a carrier frequency of 2.5 GHz in 64QAM OFDM systems. Under this condition, the system performance has less than 0.8 dB design loss in terms of PER and is shown to have more than 10 dB improvement compared with the reference design.

Estimation of Carrier Frequency Offset With I/Q Mismatch Using Pseudo-Offset Injection in OFDM Systems

This work presents a novel carrier frequency offset (CFO) estimation algorithm, based on pseudo-CFO (P-CFO), to estimate the CFO value under the conditions of I/Q mismatch for direct conversion structures with 2-dB gain error and 20-deg. phase error in frequency selective fading channels. To circumvent CFO with I/Q mismatch, the proposed P-CFO algorithm rotates three training symbols by adding extra frequency offset into the received sequence to improve CFO estimation. Simulation results indicate that the estimation error of the proposed method is about 0.3 ppm, which is lower than those of two-repeat preamble-based methods. Additionally, the proposed P-CFO algorithm is compatible with the conventional method, and is appropriate for SoC implementation. The proposed scheme is implemented as part of an orthogonal frequency-division multiplexing wireless receiver fabricated in a 0.13-mum CMOS process with 3.3 times 0.4 mm2 core area and 10-mW power consumption at 54-Mbits/s data rate.

Design of a wide-band frequency synthesizer based on TDC and DVC techniques

A wide-band frequency synthesizer based on time-to-digital (TDC) and digital-to-voltage (DVC) conversion techniques is proposed here. The proposed frequency synthesizer has the capabilities of jitter reduction and large bandwidth, making it more robust for high-frequency applications. A test chip is designed and fabricated in 0.6-/spl mu/m CMOS single-poly triple-metal process. Here, the novel DVC circuit is realized by tristate inverters, where the resolution can achieve 0.2 mV. Control stability of jitter can improve about 24 dB by exploiting the TDC-based controller. In order to achieve high output frequency and large output range, an analog voltage-controlled oscillator is designed to provide a locked range from 900 to 1900 MHz with <22 kHz resolution at 3.3 V. Simulation and test results show that the proposal can work as expected. Moreover, the TDC-based controller can be treated as soft IP to speed up turnaround time.

A Cost-Effective Preamble-Assisted Engine With Skew Calibrator for Frequency-Dependent I/Q Imbalance in 4

Variations in I/Q gains, phases, and filters of the RF frontend, namely frequency-dependent I/Q imbalance (FDI), are an important factor in OFDM-based wireless access. To enable the proper function of a 4 × 4 MIMO-OFDM receiver this work proposes a low-complexity preamble-assisted solution using only one complex divider and one complex multiplier to handle significant FDI distortions. An all-digital multiphase and multi-rate clock generator (MPRCG) was built to support fast dynamic frequency scaling for FDI estimation and compensation and for efficient implementation. Based on the proposed MPRCG, a skew calibration was also realized to tune I/Q timing coherently via multiphase A/D clocking. Performance evaluation showed that the proposed approach incurs an SNR loss of 1.5 dB to maintain a packet-error rate of less than 10% under a 1 dB gain error, 15 phase error and worse filter mismatch. Thus, this solution not only provides adequate performance, but also makes FDI estimation and compensation more cost-effective.

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In this paper, the algorithm of a VLC codec system with new group-based approach is presented. Based on the proposed codeword grouping and symbol memory mapping, the group-searching scheme and codec processes are completed by applying numerical properties and arithmetic operations to codewords and symbol addresses. The memory requirement of encoder is reduced by a novel symbol-converting scheme. Therefore, the programmable coding table and symbol representation can be achieved. Based on MPEG-like systems, an architecture design that performs concurrent VLC codec processes with constant symbol rate is presented. Simulation results show 100 Msps with 100 MHz-clock for both encoding/decoding procedures can be achieved. As a result, it is suitable for those applications that require codec processes simultaneously, such as videoconferencing, and high throughput systems, such as HDTV.

4 MIMO-OFDM Modem

In this paper, a single instruction multiple data (SIMD) arithmetic logic unit (ALU)-based architecture is proposed to improve hardware efficiency in a 4 × 4 frequency-domain multiple input multiple output-orthogonal frequency division multiplexing modem based on a space-time block code (STBC). The majority of mathematic units in the proposed architecture are centralized so that any mathematic unit can be shared with any algorithm. Six advanced instructions are also defined in the ALU: 1) complex multiplication; 2) complex division; 3) correlation; 4) channel estimation; 5) 4 × 4 matrix inversion; and 6) STBC-based decoding. A scheduler is essential to handle all data paths and signaling flows smoothly with the use of an SIMD ALU. As a result, it is relatively easy to reconfigure the proposed design for different specifications. The very large scale integration implementation of this chip, using an in-house 65-nm CMOS process, consumes a total of 1.87 M gates and draws 33.7 mW at a supply voltage of 1 V.

A new approach of group-based VLC codec system

This paper presents an all-digital standard cell SR-Latch based time amplifier (TA) with a variable gain of 6X and 12X. In this TA, a two-stage gain selection unit is applied to enable the TA to select either the high gain for short input pulse intervals or the low gain for long input pulse intervals. The time amplification gain is 6 in the input range of -700ps ~700ps, and reaches 12 if the input range is -300~300ps. We present a design that automatically detects the input pulse and switches to the proper TA gain. By applying the proposed TA, a standard cyclic TDC implemented in a UMC CMOS 65-nm process shows the resolution improved from 1.6ps to 0.8 ps.

Cost-Efficient Frequency-Domain MIMO–OFDM Modem With an SIMD ALU-Based Architecture

In this paper, a frequency domain equalizer is proposed for WLAN 802.11g single-carrier transmission mode. Channel estimation is achieved with a modified recursive least square (RLS) algorithm in the frequency domain. For channel compensation, OFDM-like frequency domain zero-forcing equalization is performed with FFT units and a complex divider. In 802.11g single-carrier mode, transmission packets are not equipped with cyclic prefixes so signal overlapping and discarding using sliding windows are maintained at each equalization process to decrease the symbol estimation error caused by circularly de-convoluting a linear channel convolution process. With the single carrier mode equalizer implemented in the frequency domain many of the computation resources can be shared with an 802.11g OFDM equalizer offering a low complexity multimode receiver solution.

A variable-gain time amplifier with automatic interval detection

This paper introduces a DSSS baseband receiver suitable for a dual mode DSSS/OFDM wireless LAN system. Packet synchroniser with a pair of ADCs with dynamic sampling is used for detecting both DSSS and OFDM packets. For differentially encoded symbols, frequency offset and phase offset can be compensated based on their inherent characteristics. For high data rate DSSS based modulations, channel estimation and equalization with receive diversity combining in frequency domain is applied to resolve the multipath distortions. With channel equalization and diversity combining of the DSSS receiver achieved in frequency domain the overall complexity of the dual mode DSSS/OFDM equalization can be realized.