Huang Lu

A 1.8 V LDO voltage regulator with foldback current limit and thermal protection

This paper introduces the design of a l.8 V low dropout voltage regulator (LDO) and a foldback current limit circuit which limits the output current to 3 mA when load over-current occurs. The LDO was implemented in a 0.18 μm CMOS technology. The measured result reveals that the LDOs power supply rejection (PSR) is about −58 dB and −54 dB at 20 Hz and 1 kHz respectively, the response time is 4 μs and the quiescent current is 20 μA. The designed LDO regulator can work with a supply voltage down to 2.0 V with a drop-out voltage of 200 mV at a maximum load current of 240 mA.

A 0.18 μm CMOS inductorless complementary-noise-canceling-LNA for TV tuner applications

This paper presents an inductorless complementary-noise-canceling LNA (CNCLNA) for TV tuners. The CNCLNA exploits single-to-differential topology, which consists of a common gate stage and a common source stage. The complementary topology can save power and improve the noise figure. Linearity is also enhanced by employing a multiple gated transistors technique. The chip is implemented in SMIC 0.18 μm CMOS technology. Measurement shows that the proposed CNCLNA achieves 13.5–16 dB voltage gain from 50 to 860 MHz, the noise figure is below 4.5 dB and has a minimum value of 2.9 dB, and the best P1dB is −7.5 dBm at 860 MHz. The core consumes 6 mA current with a supply voltage of 1.8 V, while the core area is only 0.2 × 0.2 mm2.

Design optimizations of phase noise, power consumption and frequency tuning for VCO

To meet the requirements of the low power Zigbee system, VCO design optimizations of phase noise, power consumption and frequency tuning are discussed in this paper. Both flicker noise of tail bias transistors and up-conversion of flicker noise from cross-coupled pair are reduced by improved self-switched biasing technology, leading to low close-in phase noise. Low power is achieved by low supply voltage and triode region biasing. To linearly tune the frequency and get constant gain, distributed varactor structure is adopted. The proposed VCO is fabricated in SMIC 0.18-μm CMOS process. The measured linear tuning range is from 2.38 to 2.61 GHz. The oscillator exhibits low phase noise of −77.5 dBc/Hz and −122.8 dBc/Hz at 10 kHz and 1 MHz offset, respectively, at 2.55 GHz oscillation frequency while dissipating 2.7 mA from 1.2 V supply voltage, which well meet design specifications.

A wideband CMOS inductorless low noise amplifier employing noise cancellation for digital TV tuner applications

A wideband inductorless low noise amplifier for digital TV tuner applications is presented. The proposed LNA scheme uses a composite NMOS/PMOS cross-coupled transistor pair to provide partial cancellation of noise generated by the input transistors. The chip is implemented in SMIC 0.18 μm CMOS technology. Measurement shows that the proposed LNA achieves 12.2–15.2 dB voltage gain from 300 to 900 MHz, the noise figure is below 3.1 dB and has a minimum value of 2.3 dB, and the best input-referred 1-dB compression point (IP1dB) is − 17 dBm at 900 MHz. The core consumes 7 mA current with a supply voltage of 1.8 V and occupies an area of 0.5 × 0.35 mm2.

A 0.18 μm CMOS Gilbert low noise mixer with noise cancellation

This paper presents a broadband Gilbert low noise mixer implemented with noise cancellation technique operating between 10 MHz and 0.9 GHz. The Gilbert mixer is known for its perfect port isolation and bad noise performance. The noise cancellation technique of LNA can be applied here to have a better NF. The chip is implemented in SMIC 0.18 μm CMOS technology. Measurement shows that the proposed low noise mixer has a 13.7–19.5 dB voltage gain from 10 MHz to 0.9 GHz, an average noise figure of 5 dB and a minimum value of 4.3 dB. The core area is 0.6 × 0.45 mm2.

An energy detection receiver for non-coherent IR-UWB

A non-coherent receiver for impulse radio ultra-wide band (IR-UWB) is presented. The proposed receiver front-end consists of a high gain LNA, a high frequency detector and an intermediate frequency (IF) amplifier to amplify the recovered signal and drive an external test instrument. To meet the requirements of high gain and a low noise figure (NF) under moderate power consumption for the LNA, capacitor cross coupled (CCC) and current reuse techniques were adopted. The detector consists of a squarer and an integrator. The overall circuit consumes 41.2 mA current with a supply voltage of 1.8 V at a 400 MHz pulse rate. The resulting energy efficiency is 0.19 nJ/pulse. A chip prototype is implemented in 0.18-?m CMOS. The die area is 2.1 ? 1.4 mm2 and the active area is 1.7 ? 0.98 mm2.

High performance QVCO design with series coupling in CMOS technology

A high performance quadrature voltage-controlled oscillator (QVCO) is presented. It has been fabricated in SMIC 0.18 μm CMOS technology with top thick metal. The proposed QVCO employed cascade serial coupling for in phase and quadrature phase signal generation. Source degeneration capacitance is added to the NMOS differential pair to suppress their flicker noise from up-conversion to close in phase noise. A dedicated low noise and high power supply rejection low drop out regulator is used to supply this QVCO. The measured phase noise of the proposed QVCO achieves phase noise of −123.3 dBc/Hz at an offset frequency of 1 MHz from the carrier of 4.78 GHz, while the QVCO core circuit and LDO draw 6 mA from a 1.8 V supply. The QVCO can operate from 4.09 to 4.87 GHz (17.5%). Measured tuning gain of the QVCO (Kvco) spans from 44.5 to 66.7 MHz/V The chip area excluding the pads and ESD protection circuit is 0.41 mm2.

A 3-5 GHz CMOS UWB power amplifier with 8 ps group delay ripple

A differential power amplifier (PA), designed using the linear-phase filter model, for a BPSK modulated ultra-wideband (UWB) system operating in the 3–5 GHz frequency range is presented. The proposed PA was fabricated using 0.18 μm SMIC CMOS technology. To achieve sufficient linearity and efficiency, this PA operates in the class-AB region, delivering an output power of 8.5 dBm at an input-1 dB compression point of −0.5 dBm. It consumes 28.8 mW, realizing a flat gain of 9.11 ± 0.39 dB and a very low group delay ripple of ±8 ps across the whole band of operation.

A 0.18 μm CMOS 3–5 GHz broadband flat gain low noise amplifier

A 3–5 GHz broadband flat gain differential low noise amplifier (LNA) is designed for the impulse radio ultra-wideband (IR-UWB) system. The gain-flatten technique is adopted in this UWB LNA. Serial and shunt peaking techniques are used to achieve broadband input matching and large gain-bandwidth product (GBW). Feedback networks are introduced to further extend the bandwidth and diminish the gain fluctuations. The prototype is fabricated in the SMIC 0.18 μm RF CMOS process. Measurement results show a 3-dB gain bandwidth of 2.4–5.5 GHz with a maximum power gain of 13.2 dB. The excellent gain flatness is achieved with ±0.45 dB gain fluctuations across 3–5 GHz and the minimum noise figure (NF) is 3.2 dB over 2.5–5 GHz. This circuit also shows an excellent input matching characteristic with the measured S11 below −13 dB over 2.9–5.4 GHz. The input-referred 1-dB compression point (IP1dB) is −11.7 dBm at 5 GHz. The differential circuit consumes 9.6 mA current from a supply of 1.8 V.

A low power high gain UWB LNA in 0.18-μm CMOS

A low power high gain differential UWB low noise amplifier (LNA) operating at 3–5 GHz is presented. A common gate input stage is used for wideband input matching; capacitor cross coupling (CCC) and current reuse techniques are combined to achieve high gain under low power consumption. The prototypes fabricated in 0.18-μm CMOS achieve a peak power gain of 17.5 dB with a –3 dB bandwidth of 2.8–5 GHz, a measured minimum noise figure (NF) of 3.35 dB and –12.6 dBm input-referred compression point at 5 GHz, while drawing 4.4 mA from a 1.8 V supply. The peak power gain is 14 dB under a 4.5 mW power consumption (3 mA from a 1.5 V supply). The proposed differential LNA occupies an area of 1.01 mm2 including test pads.