Huang-Siang Lan

Strain-enhanced photoluminescence from Ge direct transition

Strong enhancement of Ge direct transition by biaxial-tensile strain was observed. The reduction in band gap difference between the direct and indirect valleys by biaxial tensile strain increases the electron population in the direct valley, and enhances the direct transition. The band gap reduction in the direct and indirect valleys can be extracted from the photoluminescence spectra and is consistent with the calculations using k⋅p and deformation potential methods for conduction bands and valence bands, respectively.

High mobility high on/off ratio C-V dispersion-free Ge n-MOSFETs and their strain response

The record high peak mobility of ∼1050 cm²/V-s on (001) Ge substrate is demonstrated in NFET. High-quality Ge/GeO<inf>2</inf> interface is ensured by rapid thermal oxidation (RTO) and remote ozone plasma treatment. The best achieved subthreshold swing is 150mV/dec and the on/off ratio is 2×10⁴. The low defective n⁺/p junction produced a record high on/off ratio of 2×10⁵, an ideality factor of 1.05 and strong electroluminescence. For the first time, it is reported that the uniaxial &#60;110> tensile strain (0.08%) on &#60;110> channel direction gives the best mobility enhancement (12%) among the different strain configurations, consistent with theoretical calculation.

Biaxial tensile strain effects on photoluminescence of different orientated Ge wafers

The enhanced photoluminescence of direct transition is observed on (100), (110), and (111) Ge under biaxial tensile strain. The enhancement is caused by the increase in electron population in the Γ valley. The shrinkage of energy difference between the lowest L valleys and the Γ valley is responsible to the population increase on (100) and (110) Ge. For (111) Ge, the energy difference increases under biaxial tensile strain but the strain decreases energy difference between the electron quasi-Fermi level and the Γ valley due to the small density of state of the lowest L valleys, and thus enhances direct recombination.

Strain response of high mobility germanium n-channel metal-oxide-semiconductor field-effect transistors on (001) substrates

Well-behaved Ge n-channel metal-oxide-semiconductor field-effect transistors on (001) substrates with dispersion-free, high on/off ratio, and high peak mobility are demonstrated. The interface trap density is effectively reduced down to 5 × 1011 cm−2 eV−1 near midgap by GeO2 passivation using rapid thermal oxidation, resulting in high peak mobility of ∼1050 cm2/Vs. The fast roll-off of the mobility at high electric field is probably due to the large surface roughness scattering. By applying uniaxial 〈110〉 tensile strain (0.08%) on 〈110〉 channel direction, the best mobility enhancement (12%) can be achieved. The calculated strain responses with proper stress configurations are consistent with experimental results.

Electron scattering in Ge metal-oxide-semiconductor field-effect transistors

The electron mobility of n-channel metal-oxide-semiconductor field-effect transistors using Ge/GeO2/Al2O3 gate stack on (001) Ge substrates is analyzed theoretically and experimentally. Phonon scattering, Coulomb scattering, and interface roughness scattering are taken into account. The Ge peak mobility exceeding Si universal in our device by a factor of 1.3 is due to the reduction of Coulomb scattering of the interface states. As compared to Si, the faster roll-off of the Ge mobility at the effective field larger than 0.3 MV/cm is due to larger interface roughness scattering.

Interfacial layer-free ZrO 2 on Ge with 0.39-nm EOT, κ∼43, ∼2×10 −3 A/cm 2 gate leakage, SS =85 mV/dec, I on /I off =6×10 5 , and high strain response

0.39-nm ultrathin EOT ZrO₂ having κ value as high as ~43 without an interfacial layer (IL) is demonstrated on Ge substrates. The EOT and gate leakage are much lower than the recent reported data [1]. In situ NH₃/H₂ remote plasma treatment (RPT) after RTO-grown ultrathin (<;1nm) GeO₂/Ge and prior to PEALD ZrO₂ leads to the formation of tetragonal phase ZrO₂ and the inhibition of GeO_x IL regrowth. As the number of RPT cycles increases, it is observed that not only higher [N] but more GeO₂ component formed on Ge surface. GeO diffuses into ZrO₂ layer via the interface reaction (Ge+GeO₂ → 2GeO) and stabilize the tetragonal phase ZrO₂. The gate dielectric has a leakage current ~10⁴X lower than other reported dielectrics in this EOT region. Ge (001) pMOSFET has low SS of 85 mV/dec and high I_on/I_off of ~6×10⁵ at V_d= -1V, while nMOSFET has SS of 90 mV/dec and I_on/I_off of ~1×10⁵ at V_d=1V. The peak electron mobility is determined by the remote phonon scattering stemming from the high-κ value. The biaxial tensile strain of ~0.04% applied on Ge (111) nMOSFET with an EOT=0.78nm produces a 4.8% drain current enhancement along the <;110> channel.

Ballistic electron transport calculation of strained germanium-tin fin field-effect transistors

The dependence of ballistic electron current on Sn content, sidewall orientations, fin width, and uniaxial stress is theoretically studied for the GeSn fin field-effect transistors. Alloying Sn increases the direct Г valley occupancy and enhances the injection velocity at virtual source node. (112¯) sidewall gives the highest current enhancement due to the rapidly increasing Г valley occupancy. The non-parabolicity of the Г valley affects the occupancy significantly. However, uniaxial tensile stress and the shrinkage of fin width reduce the Г valley occupancy, and the currents are enhanced by increasing occupancy of specific indirect L valleys with high injection velocity.

Asymmetric Keep-Out Zone of Through-Silicon Via Using 28-nm Technology Node

The performance variation caused by the stress field near a through-silicon via (TSV) is measured using 28-nm node devices across 12-in wafers. The TSV is fabricated by a via-last process. The back-end-of-line dielectrics on TSV cause the asymmetric stress field, i.e., the absolute value of radial stress (|σr|) does not equal to that of tangential stress (|σθ|) on silicon and leads to the asymmetric keep-out zone (KOZ), different from previously reported. A modified KOZ model with the asymmetric radial and tangential stress field is proposed and verified by 3-D finite-element analysis simulation and experiment data. The physics behind the asymmetry is also described. Comparable KOZ size for nFETs and pFETs is observed.

In-situ doped and tensily stained ge junctionless gate-all-around nFETs on SOI featuring I on = 828 µA/µm, I on /I off ∼ 1×10 5 , DIBL= 16–54 mV/V, and 1.4X external strain enhancement

In-situ CVD doping and laser anneal can reach [P] and tensile strain as high as 2×10²⁰ cm^-3 and 0.34%, respectively, in Ge on SOI with low defect density and high activation rate (nearly 100% near the surface), and enables high performance of the junctionless (JL) Ge gate-all-around (GAA) nFETs. The device with the W_fin of 13 nm, EOT of 10 nm, and nominal L_G of 280 nm has I_on = 350 μA/μm, I_on/I_off = 3×10⁶, SS = 185 mV/dec, and DIBL = 16 mV/V. The device with the W_fin of 9 nm and EOT of ~ 0.8 nm achieves the record high I_on of 828 μA/μm at V_GS - V_T = 1.5 V and V_DS = 2 V with DIBL = 54 mV/V, I_on/I_off = 1×10⁵ and SS = 150 mV/dec. Besides the epitaxial tensile strain (0.34%) generated by laser anneal due to the misfit of thermal expansion coefficients between Ge and Si, the enhanced tensile strain by the microbridge structure is also beneficial for I_on. The drain current enhancement of ~40% is achieved under the mechanical uniaxial tensile strain of ~0.25% due to sub-band splitting and carrier repopulation into the L4 valleys with the small conductive effective mass. The non-uniform shape of Ge channel with a minimum width at the center leads to enhanced I_on as compared to uniform channel. The extracted mobility of JL devices increases with increasing temperature, indicating the domination of impurity scattering. The threshold voltage of JL devices has the negative temperature coefficient and EOT scaling reduces the temperature dependence.

Compact modeling and simulation of TSV with experimental verification

Impact of via-last through-silicon via (TSV) on 28nm node devices is investigated. The stress field of TSV is affected by the back-end-of-line (BEOL) dielectrics. The absolute value of radial stress (|σr|) is different from that of tangential stress (|σθ|) on silicon, which leads to the asymmetric keep-out zone (KOZ). The physics behind the asymmetry is also described. A modified KOZ model considering the asymmetric stress field is proposed and verified by experiment data.