Sun-Rong Jan

Mechanically strained strained-Si NMOSFETs

The drain-current enhancement of the mechanically strained strained-Si NMOSFET device is investigated for the first time. The improvements of the drain current are found to be /spl sim/3.4% and /spl sim/6.5% for the strained-Si and control Si devices, respectively, with the channel length of 25 /spl mu/m at the external biaxial tensile strain of 0.037%, while the drain-current enhancements are /spl sim/2.0% and /spl sim/4.5% for strained-Si and control Si devices, respectively, with the channel length of 0.6 /spl mu/m. Beside the strain caused by lattice mismatch, the mechanical strain can further enhance the current drive of the strained-Si NMOSFET. The strain distribution due to the mechanical stress has different effect on the current enhancement depending on the strain magnitude and channel direction. The smaller current enhancement for strained-Si device as compared to the control device can be explained by the saturation of mobility enhancement at large strain.

Strained Pt Schottky diodes on n-type Si and Ge

In summary, the reduction of the Schottky-barrier height for the n-type semiconductor under external mechanical strain is observed. This reduction is shown to originate from the reduction of conduction band edge. The boundary condition under uniaxial strain technology is stress-free along the direction perpendicular to uniaxial stress obtain the reasonable agreement between data and theoretical calculation

Mechanically strained Si-SiGe HBTs

The current gain (/spl beta/=I/sub C//I/sub B/) variations of the mechanically strained Si-SiGe heterojunction bipolar transistor (HBT) and Si bipolar junction transistor (BJT) devices are investigated experimentally and theoretically. The /spl beta/ change of HBT is found to be 4.2% and -7.8 under the biaxial compressive and tensile mechanical strain of 0.028%, respectively. For comparison, there are 4.9% and -5.0 /spl beta/ variations for BJT under the biaxial compressive and tensile mechanical strain of 0.028%, respectively. In HBT, the mechanical stress is competing with the compressive strain of SiGe base, inherited from the lattice misfit between SiGe and Si. The current change due to externally mechanical stress is the combinational effects of the dependence of the mobility and the intrinsic carrier concentration on strain.

Biaxial tensile strain effects on photoluminescence of different orientated Ge wafers

The enhanced photoluminescence of direct transition is observed on (100), (110), and (111) Ge under biaxial tensile strain. The enhancement is caused by the increase in electron population in the Γ valley. The shrinkage of energy difference between the lowest L valleys and the Γ valley is responsible to the population increase on (100) and (110) Ge. For (111) Ge, the energy difference increases under biaxial tensile strain but the strain decreases energy difference between the electron quasi-Fermi level and the Γ valley due to the small density of state of the lowest L valleys, and thus enhances direct recombination.

A Compact Analytic Model of the Strain Field Induced by Through Silicon Vias

The thermoelastic strains are induced by through silicon vias due to the difference of thermal expansion coefficients between the copper ( ~ 18 ppm / °C) and silicon ( ~ 2.8 ppm /°C) when the structures are exposed to a thermal ramp in the process flow. A compact analytic model (Bessel function) of the strain field is obtained using Kane-Mindlin theory, and has a good agreement with the finite-element simulations. The elastic strains in the silicon in the radial direction and angular direction are tensile and compressive, respectively. The linear superposition of the analytic model of a single via can be used in the multi-via configuration. Due to the interaction of vias, the slightly larger errors of strain occur between the two close vias when the linear superposition is used.

Influence of defects and interface on radiative transition of Ge

The influences of defects and surface roughness on the indirect bandgap radiative transition of Ge were studied. Bulk Ge has 15 times the integrated intensity of photoluminescence of Ge-on-Si. However, for Ge-on-Si sample, the direct transition related photoluminescence intensity is higher than the indirect transition related one. We affirm that the defects in the Ge-on-Si are responsible for the weak indirect transition and relatively strong direct transition. The scattering of electrons by roughness at Ge/oxide interface can provide extra momentum of the indirect band transition of Ge, and thus enhance the indirect radiative transition.

Buckled SiGe layers by the oxidation of SiGe on viscous SiO2 layers

SiGe-on-insulator structures have been fabricated by wafer bonding and layer transfer techniques. The relaxation process of the compressively strained SiGe films bonded to SiO2 layers through the rapid thermal oxidation was investigated. Buckling nucleus were randomly located at the beginning of oxidation and the buckling undulation was well developed after 30s oxidation at 960°C. The buckling amplitude increases with the increasing thermal oxidation time. An emission peak at 1.5μm was observed in the low temperature photoluminescence of the buckled SiGe layers.

Asymmetric Keep-Out Zone of Through-Silicon Via Using 28-nm Technology Node

The performance variation caused by the stress field near a through-silicon via (TSV) is measured using 28-nm node devices across 12-in wafers. The TSV is fabricated by a via-last process. The back-end-of-line dielectrics on TSV cause the asymmetric stress field, i.e., the absolute value of radial stress (|σr|) does not equal to that of tangential stress (|σθ|) on silicon and leads to the asymmetric keep-out zone (KOZ), different from previously reported. A modified KOZ model with the asymmetric radial and tangential stress field is proposed and verified by 3-D finite-element analysis simulation and experiment data. The physics behind the asymmetry is also described. Comparable KOZ size for nFETs and pFETs is observed.

Thermal resistance modeling of back-end interconnect and intrinsic FinFETs, and transient simulation of inverters with capacitive loading effects

A two-step pseudo isothermal plane model is used to calculate the thermal resistance of BEOL (Rth, beol). The intrinsic thermal resistances of 14nm FinFETs (Rth0, Device) are extracted with face-up (conventional measurement, heat flow from the channel to substrate) and face-down (flip-chip, heat flow from the channel to metal contact) configurations. Since the free convection of air has a large thermal resistance, the heat flow direction affects Rth0, Device. The face-up Rth0, Device is higher than face-down Rth0, Device. This is more significant for multi-finger FinFETs. The volume of hot spot affects the cooling time. In an inverter, the maximum temperature (Tmax) of pFET is higher than nFET due to the low thermal conductivity of SiGe S/D. Tmax and the high temperature duration can be controlled by the current and output capacitive loading of the inverter. The residual temperature in the channel and the temperatures of M1 layer are found too low to reflect the real device temperature, which may lead to an underestimation of device temperature with transient AC input.

Blue Electroluminescence From Metal/Oxide/6H-SiC Tunneling Diodes

The tunneling current of Pt/oxide/n-6H-SiC tunneling diodes was used for electroluminescence (EL). The negative gate bias can inject electrons from Pt to n-SiC and leads to a radiative donor-acceptor pair (DAP) transition. The blue EL at room temperature is observed at negative gate bias, and the intensity increases with increasing drive current. The DAP transition is enhanced by the electric field due to carrier tunneling. Thus, strong luminescence is observed at negative (inversion) bias, while no luminescence is observed at positive (accumulation) bias.