Huaping Jiang

Proposal of a GaN/SiC Hybrid Field-Effect Transistor for Power Switching Applications

A GaN/SiC hybrid field-effect transistor (HyFET) is proposed as a high-voltage power device that provides a high-mobility lateral AlGaN/GaN channel to reduce the channel resistance and a vertical SiC drift region to sustain the high OFF-state voltage. The performance of the HyFET is evaluated by numerical device simulations. Compared with the conventional SiC MOSFET, the HyFET exhibits a greatly reduced R_ON together with a low C_GD and low gate charges. The figures of merit Q_G × R_ON and Q_GD × R_ON of the HyFET are dramatically improved.

Low ON-Resistance SiC Trench/Planar MOSFET With Reduced OFF-State Oxide Field and Low Gate Charges

We propose a SiC trench/planar MOSFET (TP-MOS) which features a trench channel and a planar channel in one half-cell. Numerical simulations with Sentaurus TCAD have been carried out to study the proposed device architecture. Compared with traditional planar MOSFET (P-MOS), the TP-MOS has a much lower RON owing to the increased channel density. Unlike traditional trench MOSFET (T-MOS) which enables a higher channel density at the price of a high bottom-oxide field in the high-voltage OFF-state, the TP-MOS features bottom p-bases as in the P-MOS that protect the gate oxide from high electric field. The OFF-state oxide field in the TP-MOS is found to be even lower than the P-MOS. In addition, the TP-MOS boasts a low feedback capacitance (Crss) and gateto-drain charge (QGD), since the coupling between the gate and the drain is suppressed by the collective effects of the top p-bases and the bottom p-bases. The QG of the TP-MOS is nearly the same as the P-MOS, and is much smaller than the T-MOS. Superior figures of merit (QG×RON and QGD×RON) are achieved in the TP-MOS.

Silicon carbide split-gate MOSFET with merged Schottky barrier diode and reduced switching loss

A silicon carbide split-gate MOSFET (SG-MOSFET) is proposed in this paper, which features a Schottky barrier diode embedded above the JFET region between the split gates. Therefore, the proposed SG-MOSFET boasts a unipolar reverse conduction path with low turn-on voltage. Additionally, the gate-to-drain charge in the proposed device is greatly reduced, owing to the presence of the Schottky anode that is shorted to the source contact. The influence of key device parameters has been studied via device simulation using Sentaurus TCAD. Comprehensive comparisons between the proposed SG-MOSFET and the conventional MOSFET are made. Apart from the superior reverse conduction characteristics, the SG-MOSFET exhibits a significant lower switching loss thanks to both the low gate-to-drain charge and the elimination of charging/discharging currents for external freewheeling diodes.

SiC Trench MOSFET With Shielded Fin-Shaped Gate to Reduce Oxide Field and Switching Loss

A silicon carbide shielded fin-shaped gate metal-oxide-semiconductor field effect transistor (SF-MOS) is proposed in this letter, which utilizes a well-grounded p-region to shield the fin-shaped trench gate. Numerical simulations by Sentaurus TCAD are carried out to study the performance of SF-MOS, and comparisons with conventional trench MOSFET and the state-of-the-art double-trench MOSFET are presented. The maximum electric field in gate oxide of the SF-MOS is effectively lowered to below 3 MV/cm, which is a widely accepted criterion for long-term gate oxide reliability. Furthermore, with the shielding effects, the gate-to-drain charge of the SF-MOS is significantly reduced, leading to lower switching loss.

Charge storage effect in SiC trench MOSFET with a floating p-shield and its impact on dynamic performances

A p-shield region under the gate trench is typically adopted in a SiC trench MOSFET for achieving lower oxide field and Crss. In this work, we comprehensively studied the impact of a floating termination at the p-shield region on device performance. The SiC trench MOSFETs internal dynamics is revealed with numerical simulations. It is found that a lloating p-shield can effectively reduce the OFF-state electric-field in the bottom gate oxide of a SiC trench MOSFET without degrading its static performance. However, during switching operation, holes would be emitted out of the floating p-shield which then becomes a region that stores negative charges. The charge storage effect could then dramatically elevate the ON-state oxide field after the device is switched from the OFF-state, and also result in slower switching speed. The stored negative charges would also narrow the ON-state current path, and consequently, the dynamic äon would be degraded.

High-speed power MOSFET with low reverse transfer capacitance using a trench/planar gate architecture

A trench/planar MOSFET (TP-MOS) is proposed in this work as a high speed switching device. The device is comprehensively studied with numerical simulations, and comparisons are made with the conventional MOSFET (C-MOS) and the split-gate MOSFET (SG-MOS). Compared to the C-MOS, the removal of the MOS-structure above the JFET region results in a dramatic reduction of the reverse transfer capacitance (Crss) in the SG-MOS and TP-MOS. The top p-base in the TP-MOS expedites the depletion in the JFET region, which helps further reduce the Crss and alleviates the electric field crowding. The additional trench channels in the TP-MOS lowers the total channel resistance, which compensates the increase of JFET resistance caused by the absence of the electron accumulation layer under the MOS-structure. Therefore, the TP-MOS achieves the best RON-Crss trade-off.

SiC MOSFET with built-in SBD for reduction of reverse recovery charge and switching loss in 10-kV applications

A silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET) for 10-kV application is proposed in this paper, which features a built-in Schottky barrier diode (SBD). Therefore, the body diode is free from activation during the third quadrant conduction state, which is beneficial for reducing the switching loss and suppressing bipolar degradation. Numerical simulations with Sentaurus TCAD are carried out to investigate the characteristics of the proposed structure in comparison to the conventional MOSFET and SBD pair. It is found that the proposed structure achieves lower reverse recovery charge and switching loss owing to three factors, i.e., faster switching speed, smaller capacitive charge, and body diode deactivation, and therefore is a superior choice for 10-kV applications.

Improved surge current capability of power diode with copper metallization and heavy copper wire bonding

Copper metallization and copper wire bonding of high power semiconductor devices have attracted growing attention in recent years due to potentially much improved reliability and increased lifetime. However, significant technical challenges still remain for its wide commercial use. Here a thick copper layer has been successfully grown onto 3300V fast recovery diodes and subsequently 16mil copper wires were used to bond the chips onto substrates. Much improved surge current performance of these copper metallized and heavy copper wire-bonded diodes over its aluminium counterpart is reported here, and the results are analysed with the help of simulation.

Proposal of a novel GaN/SiC hybrid FET (HyFET) with enhanced performance for high-voltage switching applications

A novel GaN/SiC HyFET is proposed as a high-voltage power switch with low ON-resistance and enhanced switching performance. The device combines the merits of SiC vertical devices and GaN lateral HEMTs by utilizing a SiC drift region to sustain high OFF-state voltage and an enhancement-mode AlGaN/GaN heterojunction channel to reduce the channel resistance. Compared with conventional SiC MOSFETs of the same voltage rating, the HyFET exhibits a greatly reduced Ron owing to the high electron mobility in the channel, together with dramatically lower Crss and QG. Furthermore, the HyFET provides a unipolar reverse conduction diode with a smaller operating voltage and superior reverse recovery property.