Ian Deviny

Silicon carbide split-gate MOSFET with merged Schottky barrier diode and reduced switching loss

A silicon carbide split-gate MOSFET (SG-MOSFET) is proposed in this paper, which features a Schottky barrier diode embedded above the JFET region between the split gates. Therefore, the proposed SG-MOSFET boasts a unipolar reverse conduction path with low turn-on voltage. Additionally, the gate-to-drain charge in the proposed device is greatly reduced, owing to the presence of the Schottky anode that is shorted to the source contact. The influence of key device parameters has been studied via device simulation using Sentaurus TCAD. Comprehensive comparisons between the proposed SG-MOSFET and the conventional MOSFET are made. Apart from the superior reverse conduction characteristics, the SG-MOSFET exhibits a significant lower switching loss thanks to both the low gate-to-drain charge and the elimination of charging/discharging currents for external freewheeling diodes.

SiC Trench MOSFET With Shielded Fin-Shaped Gate to Reduce Oxide Field and Switching Loss

A silicon carbide shielded fin-shaped gate metal-oxide-semiconductor field effect transistor (SF-MOS) is proposed in this letter, which utilizes a well-grounded p-region to shield the fin-shaped trench gate. Numerical simulations by Sentaurus TCAD are carried out to study the performance of SF-MOS, and comparisons with conventional trench MOSFET and the state-of-the-art double-trench MOSFET are presented. The maximum electric field in gate oxide of the SF-MOS is effectively lowered to below 3 MV/cm, which is a widely accepted criterion for long-term gate oxide reliability. Furthermore, with the shielding effects, the gate-to-drain charge of the SF-MOS is significantly reduced, leading to lower switching loss.

SiC MOSFET with built-in SBD for reduction of reverse recovery charge and switching loss in 10-kV applications

A silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET) for 10-kV application is proposed in this paper, which features a built-in Schottky barrier diode (SBD). Therefore, the body diode is free from activation during the third quadrant conduction state, which is beneficial for reducing the switching loss and suppressing bipolar degradation. Numerical simulations with Sentaurus TCAD are carried out to investigate the characteristics of the proposed structure in comparison to the conventional MOSFET and SBD pair. It is found that the proposed structure achieves lower reverse recovery charge and switching loss owing to three factors, i.e., faster switching speed, smaller capacitive charge, and body diode deactivation, and therefore is a superior choice for 10-kV applications.

Improved surge current capability of power diode with copper metallization and heavy copper wire bonding

Copper metallization and copper wire bonding of high power semiconductor devices have attracted growing attention in recent years due to potentially much improved reliability and increased lifetime. However, significant technical challenges still remain for its wide commercial use. Here a thick copper layer has been successfully grown onto 3300V fast recovery diodes and subsequently 16mil copper wires were used to bond the chips onto substrates. Much improved surge current performance of these copper metallized and heavy copper wire-bonded diodes over its aluminium counterpart is reported here, and the results are analysed with the help of simulation.

Study of failure mechanism in the modern IGBT with a highly doped N-buffer layer

Modern IGBT structure with a highly doped buffer layer showed a MOSFET-like behavior at low collector-emitter voltage when the gate was fully turned-on. This significantly increased the conduction loss and resulted in scrap chips. Its failure mechanism has been systematically studied in this paper to reveal the underlying device physics inside the IGBT microstructure using energy-band theory, numerical simulation and equivalent circuit methods. It is reported that both tunneling current and low injection efficiency of highly doped p-emitter/n-buffer junction are root causes, and the latter deactivates the bipolar function, so that the device is dominated by MOSFET action only under low collector-emitter voltage condition. The paper will be concluded by presenting excellent measured performances of IGBTs using optimized p-emitter/n-buffer junction.

Effect of Design Variations and N2O Annealing on 1.7kV 4H-SiC Diodes

In this work we have studied the influence of design and process variations on electrical performance of 1.7 kV 4H-SiC Schottky diodes. Diodes with two variations in their active region design namely, stripe design and segment design, were fabricated in this study. Field Limiting Rings (FLRs) or Junction Termination Extension (JTE) were used as edge termination design to achieve a blocking voltage of 1.7 kV. In addition to these designs an extra processing step of nitrous oxide (N2O) annealing was performed on some of the diodes. The study has shown that there is no extra beneficial effect of nitrous oxide annealing on device characteristics.

A novel 1700V RET-IGBT (recessed emitter trench IGBT) shows record low V CE(ON) , enhanced current handling capability and short circuit robustness

In this paper, a novel 1700V recessed emitter trench IGBT (RET-IGBT) is proposed. The RET-IGBT features an additional recessed trench between two adjacent active trenches and under the emitter contact, which reduces the drawn trench to trench separation from 6μm to 2μm. Combined with a double-dose carrier storage (CS) layers, the injection enhancement effect is enhanced. As a result, the trade-off relationship between Vce(on) and £off is improved. The fabricated RET-IGBT shows record low Vce(on) of 1.65V at 150A(110A/cm−2), no degradation in breakdown voltage and short circuit performances whilst enhancing the current handling capability in spite of increased current density.

Optimum Design of 4H-SiC Junction Barrier Schottky Diode with Consideration of the Anisotropic Impact Ionization

Optimum n-drift region of a 4H-SiC Junction Barrier Schottky Diode (JBS) was analyzed by simulation with consideration of the anisotropic impact ionization. According to the detailed simulations using SRIM and Sentaurus, model parameters of empirical equations were obtained through fitting, which showed that the anisotropic avalanche model (2D-ANISO) differs significantly from the 1-dimensional empirical model (1D-Cooper) and the old isotropic avalanche model (2D-ISO). These initial results suggested that the JFET resistance and anisotropic impact ionization should be taken into account during the optimization of a 4H-SiC JBS in which field crowding at the corner of p-grid causes higher reverse leakage current.

Process development and proton implanted n-type buffer optimization for 1700V rated thin wafer fast recovery diodes

Developing suitable processes for thin wafer fast recovery power diodes is important for modern production plants as the substrate dimension increases. A set of emerging technologies has been employed here in order to fabricate 1700V rated fast recovery diodes from standard Si IGBT substrates without pre-diffused backside n-type buffer. Wafer grinding, n+ back surface contact implant, laser annealing and multiple proton implantations were all employed here for the diode fabrication. Detailed processing parameters for each step were carefully selected and optimized for the fabrication. Both SRIM and Silvaco simulations were carried out to initially provide theoretical guide for experimental design and later compared with measured results. The fabricated diodes were tested under both static and dynamic recovery conditions. The results demonstrate that the processing technologies used here are capable of making fast recovery diodes from standard IGBT substrates.