Huaxi Gu

A low-power fat tree-based optical network-on-chip for multiprocessor system-on-chip

Multiprocessor system-on-chip (MPSoC) is an attractive platform for high-performance applications. Networks-on-Chip (NoCs) can improve the on-chip communication bandwidth of MPSoCs. However, traditional metallic interconnects consume significant amount of power to deliver even higher communication bandwidth required in the near future. Optical NoCs are based on CMOS-compatible optical waveguides and microresonators, and promise significant bandwidth and power advantages. This paper proposes a fat tree-based optical NoC (FONoC) including its topology, floorplan, protocols, and a low-power and low-cost optical router, optical turnaround router (OTAR). Different from other optical NoCs, FONoC does not require building a separate electronic NoC for network control. It carries both payload data and network control data on the same optical network, while using circuit switching for the former and packet switching for the latter. The FONoC protocols are designed to minimize network control data and the related power consumption. An optimized turnaround routing algorithm is designed to utilize the low-power feature of OTAR, which can passively route packets without powering on any microresonator in 40% of all cases. Comparing with other optical routers, OTAR has the lowest optical power loss and uses the lowest number of microresonators. An analytical model is developed to characterize the power consumption of FONoC. We compare the power consumption of FONoC with a matched electronic NoC in 45 nm, and show that FONoC can save 87% power comparing with the electronic NoC on a 64-core MPSoC. We simulate the FONoC for the 64-core MPSoC and show the end-to-end delay and network throughput under different offered loads and packet sizes.

A Low-power Low-cost Optical Router for Optical Networks-on-Chip in Multiprocessor Systems-on-Chip

Networks-on-chip (NoCs) can improve the communication bandwidth and power efficiency of multiprocessor systems-on-chip (MPSoC). However, traditional metallic interconnects consume significant amount of power to deliver even higher communication bandwidth required in the near future. Optical NoCs are based on optical interconnects and optical routers, and have significant bandwidth and power advantages. This paper proposed a high-performance low-power low-cost optical router, Cygnus, for optical NoCs. Cygnus is non-blocking and based on silicon microresonators. We compared Cygnus with other microresonator-based routers, and analyzed their power consumption, optical power insertion loss, and the number of microresonators used in detail. The results show that Cygnus has the lowest power consumption and losses, and requires the lowest number of microresonators. For example, Cygnus has 50% less power consumption, 51% less optical power insertion loss, and 20% less microresonators than the optimized traditional optical crossbar router. Comparing to a high-performance 45nm electronic router, Cygnus consumes 96% less power. Moreover, the passive routing feature of Cygnus guarantees that, while using dimension order routing algorithm, the maximum power consumption to route a packet through a network is a small constant number, regardless of the network size. For example, the maximum power consumption is 4.80fJ/bit under current technologies. We simulated and analyzed an 8x8 2D mesh NoC built from Cygnus and showed the end-to-end delay and network throughput under different offered loads and packet sizes.

A novel optical mesh network-on-chip for gigascale systems-on-chip

Nanoscale CMOS technologies are posing new network-on-chip (NoC) concepts to gigascale system-on-chip (SoCs). However, electronic network on chip designs face several problems like energy consumption, bandwidth and latency. Optical NoC (ONoC) promises to solve these problems. The advances in nanoscale photonic technology make ONoCs possible. This paper proposes a new non-blocking optical router, OXY, and uses it to build a 2D mesh ONoC. OXY based optical mesh NoC fully utilizes the properties of XY routing in 2D networks, and significantly reduce the number of microring resonators required for ONoCs. We compared OXY based optical mesh NoC with three other schemes in number of microring resonators, loss and energy consumption. The results show that OXY based optical mesh NoC achieves the best in all the comparisons. We simulated 2D optical mesh ONoC based on OXY, and showed the end-to-end delay and throughput under different traffic loads and network sizes.

ODOR: a microresonator-based high-performance low-cost router for optical networks-on-Chip

The performance of system-on-chip is determined not only by the performance of its functional units, but also by how efficiently they cooperate with one another. It is the on-chip communication architecture which determines the cooperation efficiency. Network-on-Chip (NoC) is introduced to improve communication bandwidth and power efficiency. However, traditional metallic interconnects consume significant amount of power to deliver large communication bandwidths. Optical NoCs are based on silicon optical interconnects with significant bandwidth and power advantages. Optical routers are the key enabling components of optical NoCs. This paper proposed a novel optical router architecture, ODOR, for optical NoCs based on XY routing algorithm. We compared ODOR with four other router architectures, and analyzed three aspects in details, including power consumption, optical power insertion loss, and the number of microresonators. The results show that ODOR has the lowest power consumption and losses and requires the least microresonators. ODOR has 40% less power consumption, 40% less loss, and 52% less microresonator than the full-connected crossbar. Furthermore, ODOR has a special feature which guarantees the maximum power to route a packet through a network to be a small constant number, regardless of the network size. The maximum power consumption is 0.96fJ/bit under current technology. We simulated a 6x6 2D mesh NoC based on ODOR, and showed the end-to-end delay and network throughput under different offered loads and packet sizes.

Distributed Flow Scheduling in Energy-Aware Data Center Networks

Recently, the strategy of powering off unneeded network devices is proposed for energy-aware data center networks (DCNs). However, efficient flow scheduling is required for balancing the load of numerous traffic flows in the irregular topologies. In this paper, we propose distributed flow scheduling (DFS) for energy-aware DCNs. DFS leverages multiple distributed schedulers and schedules elephant flows to suitable routes. Compared with previous solutions, DFS achieves ideal network performance with better scalability and efficiency. Finally, the evaluations demonstrate that DFS is a feasible system to be implemented in energy-aware DCNs.

An energy- and buffer-aware fully adaptive routing algorithm for Network-on-Chip

Routing algorithms play a significant role in high performance Network-on-Chip which has been widely applied as an efficient communication paradigm for large System-on-Chip. However, existing routing algorithms largely neglect the imbalanced thermal distribution which leads to high temperature nodes. In this paper, an energy- and buffer-aware fully adaptive routing algorithm (EBAR) is proposed to balance the thermal distribution and satisfy the performance requirements. A network state function model, which takes both historical and current states of network into consideration, is constructed to balance the distribution of thermal and alleviate the network congestion. In the meanwhile, a new thermal management scheme is proposed to lower the temperature and satisfy the performance requirements of high priority packets. The simulation results show that EBAR can provide improvement in thermal distribution without performance degradation. The improvements of end-to-end delay and throughput also demonstrate the advantages that can be provided by EBAR.

DTBR: A dynamic thermal-balance routing algorithm for Network-on-Chip

Network-on-Chip (NoC) replaces the traditional bus-based architecture to become the mainstream design methodology for future complex System-on-Chip (SoC). It introduces the principles of packet switching and interconnection network into SoC design, and achieves much better performance for its high bandwidth, scalability, reliability, etc. However, thermal problem, such as regional temperature differential and hotspot, is still one of the main designing constraints. This paper proposes a dynamic thermal-balance routing (DTBR) algorithm for Network-on-Chip, which can solve both of the two thermal problems. DTBR is a minimal adaptive routing algorithm based on an architectural thermal model. An efficient thermal-aware router is designed to implement the DTBR algorithm. According to the simulation results, the proposed DTBR algorithm can make the network thermal distribution more uniform and hotspot temperature is cut down about 20% in different traffic patterns. Moreover, DTBR will bring a profit for the performance of packet delay and network throughput compared with other routing algorithms.

Low Latency and Energy Efficient Optical Network-on-Chip Using Wavelength Assignment

Optical network-on-chip (ONoC) is a promising technology for high-performance and energy-efficient intra-chip interconnection. Many existing proposals resort to high-density wavelength division multiplexing (WDM) to increase bandwidth and to mitigate contention. Unfortunately, high-density WDM increases the cost of optical devices and the difficulties of integration. We propose WANoC, a novel ONoC design with careful wavelength assignment aimed at more effective reuse. A novel WDM optical router is also designed with simple layout, which needs fewer waveguides and has fewer crossings. The simulation results show that the saturation load is improved more than 2.7 times, while the energy consumption is decreased by 33% compared with prior circuit-switched ONoC.

A Novel Two-Layer Passive Optical Interconnection Network for On-Chip Communication

Passive optical interconnection network (OIN) plays a key role in optical Network-on-Chip (ONoC) architecture. Existing passive OINs based on wavelength division multiplexing (WDM) are popularly employed. However, the scalability of these passive OINs is limited by the number of wavelengths and large insertion loss induced by the waveguide crossings. In this paper, we propose a novel Passive OIN based on two-layer architecture, POINT, for ONoC architecture. POINT leverages space division multiplexing (SDM) to assist WDM in eliminating blocking. The inter-layer communication in POINT relies on the inter-layer coupler, which contributes to reduce crossing losses. POINT features a modular and scalable design, in which the proposed SDM-based cell (SBC) is used as the basic building block to construct POINT with efficient wavelength assignment. Furthermore, SBCs of different sizes provide different options for constructing POINT. Comparisons with existing passive OINs confirm that POINT can provide an optimal choice with the balance between the number of wavelengths, area overhead, and insertion loss for the same size.

A Hierarchical Optical Network-On-Chip Using Central-Controlled Subnet and Wavelength Assignment

Optical network-on-chip (ONoC) is a promising alternative to be served as the fundamental architecture for future many-core system. However, several problems of ONoC, such as power consumption, arbitration overhead, and device cost, pose many limitations to the architecture design. In this paper, a novel hierarchical ONoC structure named CWNoC is proposed, which is a 256-core architecture composed of multiple central-controlled subnets. It reduces the network complexity by dividing the whole network into several subnets and lowers the arbitration overhead by adopting centralized arbitration logic in each subnet. An efficient wavelength assignment method, making full use of broadband microring resonators, is also employed in CWNoC, which facilitates simplifying the optical layer and reducing the possibility of contention. The simulation results show that CWNoC has a better latency and power consumption performance. For example, when low and medium load is applied, the latency reduction can be as much as 40 ns compared with WANoC, while the total power consumption is reduced by 70%.