Yintang Yang

A low voltage bulk-driving PMOS cascode current mirror

Based on the bulk driven PMOS transistor, a low voltage CMOS cascade current mirror (BDCCM) is presented, then the input/output impedance and frequency characteristics are discussed. Based on the simulation and test results of the TSMC 0.25 ¿m 2P4M CMOS process, the minimal input voltage of BDCCM is about 0.3 V. Comparing BDCCM with gate driven cascade current mirror (GDCCM), the input/output linear characteristics and frequency width of BDCCM is lower. So the BDCCM is a good block for low voltage low frequency CMOS analog integrated circuits.

A high-speed asynchronous array multiplier based on multi-threshold semi-static NULL convention logic pipeline

This paper proposes an asynchronous 12 × 12 -bit array multiplier. Firstly, we proposed a new asynchronous pipeline of which data processing and completion detection can be carried out simultaneously by applying multi-threshold semi-static NCL (MTSNCL) to asynchronous combinational logic. Sencondly, the pipeline is used for designing an asynchronous 12 × 12 -bit array multiplier. Finally, both the proposed array multiplier and the original array multiplier are simulated based on SMIC 0.18-µm CMOS technology. Compared with the general asynchronous array multiplier, the new array multiplier has 76.5% higher throughput, 43.8% lower TDD cycle time and 38.7% lower static power consumption. The multi-threshold array multiplier is suitable for high-speed lower-power asynchronous multiplier design.

A thermal model for the top layer of 3D integrated circuits considering through silicon vias

Based on the analytical thermal model for the top layer of three-dimensional integrated circuits (3D ICs) without through silicon vias (TSVs), the corresponding analytical thermal model taking TSVs into account is proposed. TSVs density ρ and effective thermal conductivity is introduced in this paper. The simulation results show that, the temperature increases sharply with the decrease of ρ for more layers and smaller ρ, and the best range of TSVs density ρ is 0.5% to 1% for an 8-layer 3D IC. These results can be effectively used as design guidelines in 3D IC thermal management studies.

Design of ultra-low voltage op amp based on quasi-floating gate transistors

The fundamental principle of quasi-floating gate (QFG) MOS transistors, along with the electrical characteristics and equivalent circuits, are discussed. Based on the PMOS quasi-floating gate transistors, an ultra-low voltage operational amplifier is proposed. With a single power supply of 0.8V, the maximal open-loop gain of the amplifier is 76.5dB, the phase margin is 62/spl deg/ and the unit gain-bandwidth is 2.98MHz with 9.45/spl mu/W power dissipation.

Experimental study on energy injection damage of a GaAs low noise amplifier with and without DC bias

An experimental study on energy injection induced damage by a pulse-modulated carrier with 300 MHz radio frequency (RF) signal source to a GaAs bipolar low noise amplifier (LNA) with and without DC bias is presented in this paper based on the measurement of the noise figure and gain variation of GaAs LNA prior to and after the energy injection. Experimental results show that the noise figures of LNA with DC bias increase obviously but the gain characteristics still retain the normal level after the energy injection. Sample dissection illustrates that the energy injection damages the collector¿s metallization so that the LNA noise increases. However, the gain characteristics of LNA without DC bias lose absolutely and the noise level increases abruptly after the energy injection because of transistors breakdown taking place between the base and the collector. Experiment results show that the noise figure of GaAs LNA is more sensitive to energy injection than gain characteristics, and due to the complexity of the effect of energy injection induced damage, it is insufficient to evaluate the damage using the gain difference as the sole parameter before and after the injection. Experiment results also indicate that the GaAs-LNA without DC bias is easier to cause functional failure of the circuit, but the damage induced even by a higher level energy injection to the GaAs-LNA with a normal DC bias is only a soft defect and does not cause any functional failure of the circuit.

A high efficiency PWM buck DC/DC converter high-level model and verification

Based on Simulink tool, the high-level model of 2.0A/375 kHz current controlling PWM buck converter is presented adopting state vector averaging method. The high-level model is verified using Beiling 2¿m/20V bipolar process and 30V/5.0A P-ch power MOSFET. The measured results show that the typical conversion efficiency can be over 90%, the maximum ripple value of output voltage is 32.8 mV, the output voltage error can be in the range of ±3%, the maximum output voltage load regulation is less than 0.3% and the PWM frequency falls to 11.01 kHz during the output circuits being shorted. The current controlling PWM buck DC/DC converter high-level model has been verified by the good performance of the 2.0A/375 kHz buck DC/DC converter.

Zero-crossing distortion analysis in one cycle controlled boost PFC for Low THD

A low-power low THD boost PFC with one cycle control is discussed. Two novel structures, the periodic self-starting timer and feedforward current control block, are introduced to reduce the zero-crossing distortion. The improved boost PFC could regulate the switch turn-on time timely according to the ac input line voltage, and reduce the distortion near the input voltage zero-crossing points significantly. The experimental THD is only 3.8%, the power factor is 0.998, the load adjust rate is 3%, the linear adjust rate is less than 1%, and the efficiency is 96.9%. Both theoretical and practical results reveal that the improved PFC meets the demands for low-power and low THD.

A novel ESD protection circuit applied in high-speed CMOS IC

A new electrostatic discharge (ESD) protection circuit based on a standard of 0.6 ¿m CMOS p-well technology has been designed and fabricated according to the request of trigger voltage, chip area and static current to high-speed CMOS IC. The new protection circuit was verified by a multi-project wafer (MPW) fabrication and tested by the transmission line pulse (TLP) generator system. The results show that new ESD protection circuit has lower trigger voltage, smaller chip area and a higher ESD failure voltage compared with those of gate grounded NMOS (ggNMOS) protection circuits with the same MPW. The voltage up to 5 KV under human-body mode (HBM) test has been obtained.

A low-kickback preamplifier with offset cancellation for pipelined folding A/D Converter

This paper presents an offset cancellation preamplifier applied to a pipelined folding A/D Converter. A simple and effective neutralization technique is implemented to reduce the kickback noise. The offset storage technique is realized with switched capacitor circuits to eliminate the effect on the resolution from input offset voltage. By Monte Carlo analysis, the preamplifier with offset variance of 3.24mV is verified operating in 200MHz sampling frequency. The dissipation power is 362µW at 1.8V with a 35×90 µm2 area in 0.18µm CMOS.

A 1.8V 100MS/s 10-bit pipelined folding A/D converter with 9.49 ENOB at Nyquist frequency

The design issues of a 10-bit 100MSample/s analog-to-digital (A/D) converter with pipelined folding architecture are described. Offset cancellation technique and resistive averaging interpolation network improve the linearity. Cascading alleviates the wide-bandwidth requirement of the folding amplifier. In 0.18µm CMOS technology, the prototype A/D converter achieves 9.49 ENOB, 58.91 dB SNDR and 74.85 dB SFDR at Nyquist frequency input and 100MHz sample clock. The INL and DNL are within ±0.48 LSB and ±0.33 LSB, respectively. The chip occupies 2.29mm2 active area and dissipates 95 mW at 1.8 V power supply.