Hugo Gicquel

Background time skew calibration for time-interleaved ADC using phase detection method

This paper presents a background time skew calibration technique for time-interleaved analog-to-digital converter (TIADC). It depends on the phase detection between a digitally generated calibration signal and the output of each ADC in the system that suffers from time skew mismatch. Digitally controlled delay lines (DCDL) are used to minimize the time skew mismatches among the clock routes. The calibration technique behaviors are theoretically analysed and verified by simulations. A 12-bit 4-channel, 800 MS/s TIADC is used as an example.

Background offset and gain calibration for time-interleaved ADC using digital sinusoidal calibration signal

This paper presents background offset and gain calibration for time-interleaved analog-to-digital converter (TIADC). The calibration technique depends on detecting the offset and the amplitude of a calibration signal. The detection is based on a simple algorithm performed in the digital part. A digital sinusoidal wave is needed to implement the calibration technique. The calibration technique behaviors are theoretically analysed and verified by simulations. A 12-bit, 4-channel, 800 MS/s TIADC is used as an example.

Foreground digital calibration of non-linear errors in pipelined A/D converters

A foreground digital calibration technique for pipelined ADC is proposed which accounts for linear error correction, while an error estimation technique for amplifier non-linearity is suggested as a reference for non-linear error correction. The calibration algorithm is based on applying a slow input to the ADC to automatically correct for linear errors, while depending on the accuracy of Digital Error Correction (DEC) to estimate and correct for non-linear errors. The proposed calibration scheme is demonstrated for an 11 bit pipelined ADC, and gives SNDR improvement over 30 dB, while using low specifications residue amplifier to reduce power consumption.

A pipelined ADC design exploration methodology employing circuit-system refinement

A pipelined ADC equation-based design space exploration methodology targeting minimum power dissipation is presented. While distinct frontiers are drawn between system-level and circuit-level design phases, this paper shows the importance of a refinement step between both phases. At the system-level, all possible architectures are examined followed by behavioral validation. Using a circuit sizing tool, different circuit topologies are investigated. The refinement phase proves to be important to increase the accuracy of system-level calculations by remapping new circuit-related parameters using the achieved circuit performances. The flow was built in an open system environment where the user has the freedom to change the modeling approach at any level, introduce different equations, and relax/tighten design constraints. An 11-bit ADC design test case is given to illustrate the methodology.