Marc Sabut

Split ADC digital background calibration for high speed SHA-less pipeline ADCs

A bottom plate sampling switch sharing technique is proposed to enable split ADC calibration with high frequency inputs for Sample and Hold Amplifier-less (SHA-less) pipeline ADCs. The shared bottom plate switch ensures that both halves of the ADC sample the input at the same time, which restores the calibration accuracy for fast varying inputs without the presence of a front-end SHA, thereby significantly reducing area and power consumption. For further power reduction, a feedforward two stage amplifier has been used to push the speed of the amplifier at lower current consumption and low supply voltage. A 12-bit 200 MS/s pipeline ADC has been designed in 40 nm CMOS technology, and the transistor level simulations of the ADC prove the efficiency of the proposed technique to restore the split ADC calibration accuracy in SHA-less pipeline ADCs.

Design considerations for low gain amplifier in the MDAC of digitally calibrated pipelined ADCs

The goal of this paper is to provide design considerations for the use of low gain amplifier presents in the Multiplying Analog-to-Digital Converter (MDAC) of pipelined ADCs with gain error correction in the digital domain. Using low gain amplifier in the MDAC makes the pipelined ADC more susceptible to gain variation and harmonic distortion, impacting the ADC performance. Theory and simulations are presented to provide design insight into the trade-off between minimum gain and its variations to preserve the calibrated ADC performance. These considerations are demonstrated on the MDAC of a 12 bit digitally calibrated pipelined ADC designed in 40nm CMOS technology.

Split ADC Based Fully Deterministic Multistage Calibration for High Speed Pipeline ADCs

A fully deterministic digital background calibration for pipeline ADCs is presented. The proposed approach is based on split ADC concept to give the shortest background calibration time with high accuracy. A slope mismatch averaging technique is employed in a multistage calibration scheme to deterministically detect the circuit errors without any iterative operations or feedback loops, which render it fast and accurate. Analysis and behavioral simulations for the developed multistage calibration demonstrate the efficiency of this technique and its merit over the LMS-based techniques. Practical considerations have been considered and the proposed calibration has been applied on a 200 MS/s 40 nm CMOS split pipeline ADC to correct for the capacitor mismatch and the amplifier finite gain. The post-layout simulation results show a very fast calibration cycle, where the ADC achieves more than 11 ENOB in less than 1600 clock cycles.

1.1-V 200 MS/s 12-bit digitally calibrated pipeline ADC in 40 nm CMOS

This paper presents a 1.1-V 200 MS/s pipeline ADC with 70 dB signal-to-noise-plus-distortion ratio (SNDR) and 54 mW power consumption. This performance is enabled by employing low gain amplifiers in the first two pipelined stages and digitally calibrate the inter-stage gain errors in the background using split ADC technique. To calibrate multistage in split ADC, Slope Mismatch Averaging (SMA) is used with a programmable-residue in the first stage. A low voltage two stage amplifier is used with feedforward compensation in its main loop and the common mode feedback (CMFB) loop to decrease the power consumption. Implemented in 40 nm CMOS, the ADC achieves more than 11 ENOB in post-layout simulation results.