Hun-Hsien Chang

Dynamic-floating-gate design for output ESD protection in a 0.35-/spl mu/m CMOS cell library

A dynamic-floating-gate design is proposed to improve ESD robustness of the driving-current-programmable CMOS output buffers in a 0.35 /spl mu/m CMOS cell library. Through suitable design to dynamically float the gates of the output NMOS/PMOS which are originally unused in a 2 mA output buffer, the ND-mode (PS-mode) ESD level of the 2 mA output buffer can be improved from the original 1.5 kV (1.0 kV) up to greater than 8 kV.

Mew diode string design with very low leakage current for using in power supply ESD clamp circuits

A new diode string design with very low leakage current is proposed for using in the on-chip power supply ESD (electrostatic discharge) clamp circuits. Three traditional designs of the stacked diode strings used in the power supply ESD clamp circuits are also fabricated in the same test chip to verify the improvement of this new design. By adding an NMOS-controlled lateral SCR (NCLSCR) device into the stacked diode string, the leakage current of this new proposed diode string with 6 stacked diodes under a 5 V (3.3 V) forward bias condition can be controlled below 2.1 (1.07) nA at an environment temperature of 125/spl deg/C. The blocking voltage of this new diode string design with NCLSCR can be linearly adjusted by simply changing the number of the stacked diodes in the diode string for application across the power lines with different voltage levels to achieve a whole-chip ESD protection scheme.