Wen-Yu Lo

Methodology on extracting compact layout rules for latchup prevention in deep-submicron bulk CMOS technology

An experimental methodology to find area-efficient compact layout rules to prevent latchup in bulk complimentary metal-oxide-semiconductor (CMOS) integrated circuits (ICs) is proposed. The layout rules are extracted from the test patterns with different layout spacings or distances. A new latchup prevention design by adding the additional internal double guard rings between input/output cells and internal circuits is first reported in the literature, and its effectiveness has been successfully proven in three different bulk CMOS processes. Through detailed experimental verification including temperature effect, the proposed methodology to extract compact layout rules has been established to save silicon area of CMOS ICs but still to have high enough latchup immunity. This proposed methodology has been successfully verified in a 0.5-/spl mu/m nonsilicided, a 0.35-/spl mu/m silicided, and a 0.25-/spl mu/m silicided shallow-trench-isolation bulk CMOS processes.

ESD protection design for 900-MHz RF receiver with 8-kV HBM ESD robustness

This paper presents a state-of-art ESD protection design for an RF circuit with a human-body-model (HBM) ESD robustness of 8 kV. By including a turn on efficient power-rails clamp circuit into the RF circuit, the ESD clamp devices of the RF input pin are operated in the forward-biased conduction, rather than the traditional junction breakdown condition Therefore, the dimension of ESD devices for the RF input pin can be further downsized to reduce the input capacitance loading for the RF signal. This design has been successfully applied in a 900-MHz RF receiver and fabricated in 0.25-/spl mu/m CMOS process with a thick top metal layer. The experimental results have confirmed that its ESD robustness is as high as >8 kV under the HBM ESD test.

ESD protection design for mixed-voltage I/O circuit with substrate-triggered technique in sub-quarter-micron CMOS process

A substrate-triggered technique is proposed to improve ESD protection efficiency of the stacked-NMOS device in the mixed-voltage I/O circuit. The substrate-triggered technique, can further lower the trigger voltage of the stacked-NMOS device to ensure effective ESD protection for the mixed-voltage I/O circuit. The proposed ESD protection circuit with the substrate-triggered technique for 2.5 V/3.3 V tolerant mixed-voltage I/O circuit has been fabricated and verified in a 0.25-/spl mu/m salicided CMOS process. Experimental results have confirmed that the HBM ESD robustness of the mixed-voltage I/O circuit can be increased /spl sim/65% by this substrate-triggered design.

New experimental methodology to extract compact layout rules for latchup prevention in bulk CMOS IC's

A new experimental methodology to find the compact layout rules on guard rings is proposed to increase latchup immunity of bulk CMOS ICs. The layout rules are extracted from the experimental test chips with latchup sensors and different drawing spacings. A new latchup prevention design with additional internal guard rings between the I/O cells and the internal circuits is first investigated in the fabricated experimental test chips. Through detailed experimental verification, including the temperature effect, one set of compact layout rules has been established to save the chip size of the pad-limited CMOS ICs but still with enough latchup immunity in a 0.5-/spl mu/m bulk CMOS technology.

Resonant phenomena in conductor-backed coplanar waveguide (CBCPW)

The resonant phenomena found in CBCPW integrated through line are investigated in detail both experimentally and theoretically. Two CBCPW through-line test circuits have been built and tested. One has uniform side planes and the other contains two slits in the middle of the side planes. Three techniques are used to investigate the resonant phenomena, namely, the patch antenna cavity model, the multimode model, and the full-wave space-domain integral equation approach. The measured transmission ( mod S/sub 21/ mod ) and reflection ( mod S/sub 11/ mod ) characteristics of the through lines are reported. At a representative resonant frequency of the measured data, current distributions are displayed, demonstrating that the side planes of the CBCPW contribute to the resonance in a way similar to planar patch antenna or 2D planar circuits.<<ETX>>

A new full-wave integral equation method for the analysis of coplanar strip circuit using the mixed-potentials eigenfunction expansion technique

Theoretical results obtained by a full-wave integral equation formulation using the mixed-potentials eigenfunction expansion technique are presented. This formulation can analyze a 3D coplanar strip discontinuity structure on a finite-width substrate. As an example of a reduced structure analyzed by the method, the theoretical results for a microstrip discontinuity problem are validated by comparing them with those obtained by the spectral-domain approach program LINMIC/sup +/.<<ETX>>

Analysis of abnormal ESD failure mechanism in high-pin-count BGA packaged ICs due to stressing non-connected balls

An abnormal failure mechanism due to ESD stressing on the Non-Connected (NC) balls of a high-pin-count (>500 balls) BGA packaged IC is presented. Failure analyses including Scanning Electronic Microscopy (SEM) photographs and the measurement of current waveform during ESD zapping had been performed to give clear explanation on this unusual phenomenon. New protection solutions have been proposed to solve this problem in a BGA packaged IC product with an improvement ESD robustness, which can sustain 3-kV HBM and 300-V MM ESD stresses.

Mew diode string design with very low leakage current for using in power supply ESD clamp circuits

A new diode string design with very low leakage current is proposed for using in the on-chip power supply ESD (electrostatic discharge) clamp circuits. Three traditional designs of the stacked diode strings used in the power supply ESD clamp circuits are also fabricated in the same test chip to verify the improvement of this new design. By adding an NMOS-controlled lateral SCR (NCLSCR) device into the stacked diode string, the leakage current of this new proposed diode string with 6 stacked diodes under a 5 V (3.3 V) forward bias condition can be controlled below 2.1 (1.07) nA at an environment temperature of 125/spl deg/C. The blocking voltage of this new diode string design with NCLSCR can be linearly adjusted by simply changing the number of the stacked diodes in the diode string for application across the power lines with different voltage levels to achieve a whole-chip ESD protection scheme.