Hung-Ju Wei

A Chebyshev-Response Step-Impedance Phase-Inverter Rat-Race Coupler Directly on Lossy Silicon Substrate and Its Gilbert Mixer Application

This paper focuses on the analysis and the design methodology of the step-impedance phase-inverter rat-race coupler on a silicon-based process. The issues of impedance limitation and bandwidth are discussed in detail. Our proposed concept utilizes a high silicon dielectric constant, phase-inverter structure, step-impedance technique, and Chebyshev response to make the rat-race coupler more compact (~ 64% reduction) and highly balanced over a wide operating bandwidth. Moreover, the inter-digital coplanar stripline used in the step-impedance section effectively reduces the characteristic impedance of the transmission line for large size shrinkage and insertion-loss reduction. The demonstrated step-impedance rat-race coupler directly on silicon substrate has 6- ~ 7-dB insertion loss from 5 to 15 GHz and small variations in amplitude/phase balance. Compared with our previous work, the proposed rat-race coupler achieves a 3-dB improvement in the insertion loss. Thus, a 0.13-μm CMOS Gilbert down-converter with a miniature phase-inverter rat-race coupler at the RF path for wideband single-to-differential signal conversion achieves a noise figure of 16 dB.

Broadband CMOS Gilbert Down-Converter utilizing a low-loss step-impedance rat-race coupler

Broadband Gilbert Down-Converter with step-impedance rat-race coupler is demonstrated using 0.13 µm standard CMOS technology. The proposed method utilizes higher effective dielectric-constant, phase-inverter and step-impedance techniques simultaneously to make the rat-race coupler more compact (∼ 64% reduction) and phase-balanced over a wide operating bandwidth. The down-converter has NF of 16 dB and LO-to-RF isolation of better than 35 dB. The mixer core consumes 2.9 mA at Vdd=1.8 V.

True 50% duty-cycle high-speed divider with the modulus of odd numbers

This paper proposes a true 50% duty-cycle high-speed prescaler with an odd modulus, based on current switchable D flip-flops. Each D flip-flop can sample data at the positive and negative clock edges, because of the changeable trigger mode. The proposed divide-by-N prescaler, with a 50% duty cycle, is formed as a ring with an N number of D flip-flops. Two types of 50% duty-cycle divide-by-five prescalers, the sample-hold-sample-hold-hold (SHSHH) prescaler and the sample-sample-hold-sample-hold (SSHSH) prescaler, are implemented using the 0.35 µm SiGe HBT technology. The SHSHH divider has a better performance, up to 7 GHz, thanks to the synchronization of data and control signals.

Broadband GaInP/GaAs HBT Regenerative Frequency Divider with Active Loads

An integrated GalnP/GaAs heterojunction bipolar transistor (HBT) regenerative frequency divider (RFD) with active loads is demonstrated at 4 GHz -26 GHz. In this work, the RFDs with resistive loads and active loads are fabricated in the same chip for comparison. From the measured results, the active-loading type obviously has wider operating frequency and lower input sensitivity. The fmax/fmin ratio of 6.5 is higher than that of general RFDs. The core power consumption is 36.7 mW at the supply voltage of 5 V. The chip size is 1.0 times 1.0 mm2.

A High-Speed HBT Prescaler Based on the Divide-by-Two Topology

This paper demonstrates the Divide-by-4/5 prescalers with merged AND gates in 2 mum GalnP/GaAs heterojunction bipolar transistor (HBT) and 0.35 mum SiGe HBT technologies. By biasing the HBT near the peak transit-time frequency (fr), the maximum operating frequency of a D-type flip-flop (D-FF) can be promoted. At the supply voltage of 5 V, the GalnP/GaAs prescaler operates from 30 MHz to 5.2 GHz, and the SiGe prescaler has the higher-speed performance of 1 GHz ~ 8 GHz at the cost of power consumption.

40-GHz high-linearity single-voltage-supply pHEMT gilbert sub-harmonic upconverter using leveled-LO topology

This paper reports a 40 GHz sub-harmonic Gilbert upconverter with a leveled-LO configuration using 0.15-µm AlGaAs/InGaAs pseudomorphic high electron mobility transistor (PHEMT) technology. The sub-harmonic structure is employed because the LO frequency is only half of the RF frequency. A two-stage RC-CR polyphase filter forms a 20-GHz quadrature generation for the LO port of the upconverter while an LC current combiner at the RF output port performs the balance-to-unbalance transformation and conversion gain enhancement. A self-biases current source is used to achieve single voltage supply. The demonstrated pHEMT sub-harmonic Gilbert upconverter has a conversion gain of −1 dB, an output return loss of −16.5 dB at 40 GHz, LO-to-RF isolation of 47 dB, and 2LO-to-RF isolation of 41 dB. OP1dB and OIP3 are −20 dBm and −5 dBm, respectively. The current consumption is 12.9 mA at a 4 V supply voltage.

12∼18 GHz resistive mixer with a miniature Marchand Balun using standard CMOS process

A 12∼18 GHz fundamental resistive mixer is demonstrated using standard 0.13 µ;m CMOS technology. A Marchand Balun directly on lossy silicon substrate is integrated with the resistive mixer to generate equal-amplitude and out-of-phase signal for LO pumping. The size of the Ku-band Marchand balun only occupies 478 µm × 250 µm due to higher silicon dielectric constant. The measured conversion loss of the resistive mixer is around 22 dB under fIF=3 GHz and PLO= 6 dBm. The small required LO power reveals that the Marchand balun does not suffer serious loss from silicon substrate. The miniature technique makes passive components more compact and easier to be integrated with IC circuit design.

A 9-GHz dual-modulus 0.18-µm CMOS prescaler using HLO-FF technique

This paper describes the design issues of the dual modulus divide-by-4/5 prescaler with merged AND gates and HLO-FF topologies fabricated in 0.18 mum CMOS technologies. By the two topologies, the propagation delay and the voltage swing can be reduced to improve the maximum operating frequency. Because the CLK transistors operate at higher frequency, how to choose the CLK transistor size and the bias current properly plays an important role. With 2.5 V supply voltage, the divide-by-4/5 prescaler can operate up to 9 GHz.

10 GHz GaInP/GaAs HBT Injection-Locked Frequency Divider

The first integrated GaInP/GaAs heterojunction bipolar transistor (HBT) injection-locked frequency divider (ILFD) with the stacked transformers is demonstrated at 9.60-10.38 GHz. The stacked transformers formed by only two metal layers provide the inductive coupling in the cross feedback and separate biasing for base and collector to allow for the larger voltage swing in the LC tank and increasing locking range. Under the supply voltage of 5 V and core power consumption of 20.5 mW, the locking range is up to 7.8% of the center operating frequency. Compared to other high frequency ILFDs employing a current source as signal injector, the design has a good performance in locking range. The chip size is 1.0 mm times 1.0 mm.

Compact GaInP/GaAs HBT Gilbert Mixers With On-Chip Active LO Balun

A Gilbert micromixer is demonstrated in this paper using GalnP/GaAs HBT technology. The RF, LO, and IF ports of the micromixer are all single-ended using the on-chip active LO balun. The port-to-port isolation has its best performance when the LO signal is balanced. The stand-along micromixer is suitable for hybrid RF system applications. The fully matched high linearity micromixer has the conversion gain of 12 dB, IPIdB of-9 dBm, IIP3 of 1 dBm when input IF=300 MHz, LO=3.5 GHz and output RF=3.8 GHz.