Jin-Siang Syu

2.4/5.7-GHz CMOS Dual-Band Low-IF Architecture Using Weaver–Hartley Image-Rejection Techniques

A 2.4/5.7-GHz dual-band Weaver-Hartley architecture, using 0.18-mum CMOS technology, is demonstrated in this paper. The 2.4-GHz signal is set to be the image signal when the desired signal is at 5.7 GHz, and vice versa. Since the Weaver and Hartley systems are combined into this architecture, the demonstrated architecture rejects not only the first image signal, but also the secondary image signal. The image-rejection ratios of the first image signal and the secondary image signal are better than 40 and 46 dB, respectively. In this paper, a diagrammatic explanation is employed to obtain the image-rejection mechanisms of the Weaver-Hartley architecture.

Large Improvement in Image Rejection of Double-Quadrature Dual-Conversion Low-IF Architectures

The reasons for a degradation of image-rejection performance in double-quadrature-double-quadrature and single-quadrature-double-quadrature dual-conversion low-IF downconverters are fully discussed in this paper. Polyphase filters (PPFs) are inserted at proper positions to minimize the effects of device/signal mismatches, and thus improve the image rejection without calibration. Both a 0.35-μm SiGe heterojunction bipolar transistor 5.2-GHz double-quadrature-double-quadrature downconverter with an RF PPF and a 0.18-μm CMOS 2.2/4.8-GHz single-quadrature-double-quadrature downconverter with a switched-band low-noise amplifier (LNA) and a narrowband inter-stage PPF are demonstrated. Compared with our previous work, the 5.2-GHz downconverter achieves a 15-dB improvement in image-rejection ratio (IRR) of the first image signal (IRR1) even without a pre-selection filter or LNA. Additionally, the dual-band downconverter has a 25-dB improvement in IRR of the second image signal (IRR2) , which nearly reaches the theoretical limit of a four-stage PPF covering 20-40 MHz.

5.7 GHz Gilbert I/Q Downconverter Integrated With a Passive LO Quadrature Generator and an RF Marchand Balun

A 5.7 GHz downconversion mixer is demonstrated in this letter using 0.35 mum SiGe BiCMOS technology. A quarter-wavelength coupled line and two center-tapped transformers are utilized to generate differential quadrature LO signals. A miniaturized Marchand balun is placed before the common-base-configured RF input stage of each Gilbert mixer to generate balanced RF signals. All the reactive passive elements are placed directly on the standard silicon substrate. The 5.7 GHz downconverter achieves 7 dB conversion gain, 26dBm 1dB, and 18dBm IIP3 at the power consumption of 3.875 mW and 2.5 V supply voltage.

A 2.4-GHz Low-Flicker-Noise CMOS Sub-Harmonic Receiver

A 2.4-GHz low-noise sub-harmonic direct-conversion receiver (SH-DCR) is demonstrated using standard 0.18-μm CMOS technology. Deep-n-well vertical-NPN (V-NPN) bipolar junction transistors (BJTs) are employed to solve the flicker noise problem in CMOS process. Design optimization of a power-constrained noise-impedance-matched low-noise amplifier (LNA) with the effect of lossy on-chip inductors is fully discussed in this paper. A multi-stage octet-phase polyphase filter is analyzed in detail and implemented to generate well balanced octet-phase LO signals. As a result, the demonstrated receiver achieves 51-dB voltage gain and 3-dB noise figure with flicker noise corner less than 30 kHz when RF = 2.4 GHz. The I/Q amplitude/phase mismatch is below ±0.2 dB/±1°, respectively, covering from 2.35 to 2.6 GHz. The dc current consumption is 5 mA at a 1.8-V supply.

Analysis and Design of the 0.13-

This paper demonstrates the design methodology of the shunt-series series-shunt dual-feedback Meyer wideband amplifier. The small-signal S-parameters are obtained for the first time using the pole-and-zero analysis, thus giving the RF designers a detailed insight into the Meyer amplifier. A 10-GHz wideband amplifier is demonstrated in this paper, using 0.13-mum CMOS technology to verify our design theory. The experimental results of the S-parameters highly agree with our theory.

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A 30 GHz trifilar-transformer-coupled quadrature voltage-controlled oscillator (QVCO) is proposed in this letter using 0.13 μm CMOS technology. The trifilar transformer provides dc decoupling as well as ac mutual coupling from drain, gate, and source nodes. The mutual coupling increases the overall quality factor while the gate/drain-to-source coupling provides quadrature coupling. The proposed 1:1:1 trifilar transformer realization has lower ohmic loss than the conventional trifilar transformer realization and is especially suitable for high-frequency applications. As a result, the proposed 30 GHz QVCO has a -195 dBc/Hz figure of merit (FOM) and a maximum 41.6 dB sideband rejection (SBR) at a 0.6 V supply.

CMOS Shunt–Series Series–Shunt Dual-Feedback Amplifier

A 2.4-GHz low-power low-noise direct-conversion receiver is demonstrated using parasitic vertical-NPN bipolar junction transistors (BJTs) in a standard 0.18-μm CMOS process. The current switching operation of a Gilbert mixer with finite transistor cutoff frequency (fT) is thoroughly analyzed and discussed in this paper. When the mixer operates near or higher than the transistor f T, the loss of the polyphase filter due to the capacitive loading of the mixer is a main issue. Thus, BJT devices with smaller base resistance and an inductive peaking technique with symmetric 3-D realization are employed in this paper to reduce local oscillator power by 4.5 dB. At 2.4 GHz, the demonstrated receiver has conversion gain of 51 dB and noise figure of 3.2 dB with 70-kHz 1/f noise corner, while the current consumption is 4.5 mA at a 1.8-V supply.

A 0.6-V 30 GHz CMOS Quadrature VCO Using Microwave 1:1:1 Trifilar Transformer

A low-power tunable-band sub-harmonic direct-conversion receiver covering the whole Unlicensed National Information Infrastructure band is demonstrated using 0.18-μm CMOS technology. The RF band is selected by tuning varactors at the loads of the two-stage low-noise amplifier, while a wideband octet- phase generator is applied at the local oscillator (LO) port. The band tuning of both an LC tank and a transformer and the de- sign of an optimal transformer turn ratio are fully discussed in this paper. Vertical-NPN bipolar junction transistors in a standard CMOS process are used at the mixer switching core for excellent 1/f noise performance. As a result, the receiver achieves a 48/50 voltage gain and 4.5/4.8-dB noise figure with a 1/f noise corner of 70 kHz when the RF band is tuned to 5.2/5.8 GHz, respectively. The dc current consumption of the RF front-end (including the LO buffer) is 8.5 mA at a 1.8-V supply.

2.4-GHz Low-Noise Direct-Conversion Receiver With Deep N-Well Vertical-NPN BJT Operating Near Cutoff Frequency

This paper proposes a true 50% duty-cycle high-speed prescaler with an odd modulus, based on current switchable D flip-flops. Each D flip-flop can sample data at the positive and negative clock edges, because of the changeable trigger mode. The proposed divide-by-N prescaler, with a 50% duty cycle, is formed as a ring with an N number of D flip-flops. Two types of 50% duty-cycle divide-by-five prescalers, the sample-hold-sample-hold-hold (SHSHH) prescaler and the sample-sample-hold-sample-hold (SSHSH) prescaler, are implemented using the 0.35 µm SiGe HBT technology. The SHSHH divider has a better performance, up to 7 GHz, thanks to the synchronization of data and control signals.

Low-Power Sub-Harmonic Direct-Conversion Receiver With Tunable RF LNA and Wideband LO Generator at U-NII Bands

A trifilar-coupling quadrature voltage-controlled oscillator (QVCO) is demonstrated using 0.35-mum SiGe heterojunction bipolar transistor (HBT) technology. The trifilar transformer consisting of one primary coil and two secondary coils is used in this work to separate the collector and base bias for output voltage swing optimization and also to replace a conventional transistor-coupling method for quadrature output generation, simultaneously. As a result, the trifilar-coupling QVCO achieves the 191.6-dBc/Hz FOM at the supply voltage of 1.2 V The on-chip passive single side-band (SSB) upconversion mixer is also demonstrated to fairly measure the quadrature accuracy of the QVCO. Consequently, the side-band rejection ratio of 37.7 dB is achieved.