Hunsoo Choo

Computation sharing programmable FIR filter for low-power and high-performance applications

This paper presents a programmable digital finite-impulse response (FIR) filter for high-performance and low-power applications. The architecture is based on a computation sharing multiplier (CSHM) which specifically targets computation re-use in vector-scalar products and can be effectively used in the low-complexity programmable FIR filter design. Efficient circuit-level techniques, namely a new carry-select adder and conditional capture flip-flop (CCFF), are also used to further improve power and performance. A 10-tap programmable FIR filter was implemented and fabricated in CMOS 0.25-/spl mu/m technology based on the proposed architectural and circuit-level techniques. The chips core contains approximately 130 K transistors and occupies 9.93 mm/sup 2/ area.

Complexity reduction of digital filters using shift inclusive differential coefficients

We present a graph theoretical methodology that reduces the implementation complexity of the multiplication of a constant vector and a scalar. The complexity of implementation is defined as the required amount of computations like additions. The proposed approach is called minimally redundant parallel (MRP) optimization and is mainly presented in a finite impulse response (FIR) filtering framework to obtain a low-complexity multiplierless implementation. The key idea is to expand the design space using shift inclusive differential coefficients (SIDCs) together with computation reordering using a graph theoretic approach to obtain maximal computation sharing. The problem is formulated using a graph in which vertices and edges represent coefficients and computational cost (number of resources). The multiplierless solution is obtained by solving a set cover problem on the vertices in the graph. A simple polynomial run time algorithm based on a greedy approach is presented. The proposed approach is compared with common-subexpression elimination to show slightly better results and is combined with it for further reduction of complexity. Simulation results show that 50-60% complexity reduction is achieved by only applying the MRP algorithm, and 70% complexity reduction is obtainable by combining it with common-subexpression elimination under a delay constraint of two or three.

High performance and low power FIR filter design based on sharing multiplication

We present a high performance and low power FIR filter design, which is based on computation sharing multiplier (CSHM). CSHM specifically targets computation re-use in vector-scalar products and is effectively used in our FIR filter design. Efficient circuit level techniques: a new carry select adder and conditional capture flip-flop (CCFF), are also used to further improve power and performance. The proposed FIR filter architecture was implemented in 0.25 μm technology. Experimental results on a 10 tap low pass CSHM FIR filter show speed and power improvement of 19% and 17%, respectively, with respect to an FIR filter based on Wallace tree multiplier.

Non-adaptive and adaptive filter implementation based on sharing multiplication

FIR filtering can be expressed as multiplication of a vector by scalars. We present high-speed implementations for adaptive and nonadaptive filters based on a computation sharing multiplier which specifically targets computation re-use in vector-scalar products. The performance of the proposed implementation is compared with implementations based on carry save and Wallace tree multipliers in 0.6 /spl mu/ technology. We show that the sharing multiplier scheme improves speed by approximately 30% and 21% with respect to the Wallace tree multiplier based implementation for non-adaptive and adaptive filters, respectively.

Two's complement computation sharing multiplier and its applications to high performance DFE

We present a novel computation sharing multiplier architecture for twos complement numbers that leads to high performance digital signal processing systems with low power consumption. The computation sharing multiplier targets the reduction of power consumption by removing redundant computations within system by computation reuse. Use of computation sharing multiplier leads to high-performance finite impulse response (FIR) filtering operation by reusing optimal precomputations. The proposed computation sharing multiplier can be applicable to adaptive and nonadaptive FIR filter implementation. A decision feedback equalizer (DFE) was implemented based on the computation sharing multiplier in a 0.25-/spl mu/ technology as an example of an adaptive filter. The performance and power consumption of the DFE using a computation sharing multiplier is compared with that of DFEs using a Wallace-tree and a Booth-encoded multiplier. The DFE implemented with the computation sharing multiplier shows improvement in performance over the DFE using a Wallace-tree multiplier, reducing the power consumption significantly.

9.1 A 45nm CMOS RF-to-Bits LTE/WCDMA FDD/TDD 2×2 MIMO base-station transceiver SoC with 200MHz RF bandwidth

Increasing mobile data demands are pushing cellular network capacity. Massive MIMO base stations with large antenna arrays and smaller cell sizes demand higher integration in radio transceivers than what is available [1].

Hardware architecture and VLSI implementation of a low-power high-performance polyphase channelizer with applications to subband adaptive filtering

The polyphase channelizer is an important component of a subband adaptive filtering system. This paper presents an efficient hardware architecture and VLSI implementation of a low-power high-performance polyphase channelizer, integrating optimizations at algorithmic, architectural and circuit level. At the algorithm level, a computationally efficient structure is derived. Tradeoffs between hardware complexity and system performance are explored during the fixed-point modeling of the system. A computational complexity reduction technique is also employed to reduce the complexity of the hardware architecture. Circuit-level optimizations, including an efficient commutator implementation, dual-VDD scheme and novel level-converting flip-flops, are also integrated. Simulation results show that the design consumes 352 mW power with system throughput of 480 million samples per second (MSPS). A test chip has been submitted for fabrication to validate the proposed hardware architecture and VLSI design techniques.

Decision feedback equalizer with two's complement computation sharing multiplication

We present an architecture of a high performance decision feedback equalizer based on a computation sharing multiplier. The computation sharing multiplier (CSHMR) uses a redundant number scheme and targets removal of computational redundancy by computation re-use. Use of CSHMR leads to high performance FIR filtering operation by re-using optimal precomputations. A decision feedback equalizer (DFE) implementation based on CSHMR in a 0.35 /spl mu/ technology shows 34% improvement in the operating speed over DFE using a Wallace tree multiplier.

Layout-driven architecture synthesis for high-speed digital filters

We propose a floorplan-aware complexity reduction methodology for digital filters. Conventional methodologies for complexity reduction use logic-centric approaches focusing on the total number of adders. Therefore, there is a need to consider interconnects to reduce communication costs while synthesizing reduced-complexity filters. In this paper, we integrate high-level synthesis and floorplan to obtain improvement in both computational complexity and interconnect delay. In our experiments, we could achieve 15% improvement in critical-path delay over conventional methodologies.

A parametric approach for low energy wireless data communication [mobile multimedia computing/communication applications]

In this paper, a joint control methodology of error protection capability and modulation strategy is presented to minimize the energy dissipation of a given communication. The communication energy includes the energy consumption of the underlying digital (channel encoder/decoder) and analog blocks including the RF amplifier. The energy dissipation of these blocks is determined by the system configuration parameters like channel coding rate, modulation order, transmission power and transmission duration. Simulation was performed on various channel qualities using the Nakagami channel model. The simulation results show that the jointly controlled communication system enhances energy efficiency. When the Nakagami fading figure is 6, 25% of the energy can be saved on average from a QPSK system with channel coding rate of 0.5. The configuration of the system should be determined considering channel quality (fading and path loss).