Charles K. Sestok

Sparse Filter Design Under a Quadratic Constraint: Low-Complexity Algorithms

This paper considers three problems in sparse filter design, the first involving a weighted least-squares constraint on the frequency response, the second a constraint on mean squared error in estimation, and the third a constraint on signal-to-noise ratio in detection. The three problems are unified under a single framework based on sparsity maximization under a quadratic performance constraint. Efficient and exact solutions are developed for specific cases in which the matrix in the quadratic constraint is diagonal, block-diagonal, banded, or has low condition number. For the more difficult general case, a low-complexity algorithm based on backward greedy selection is described with emphasis on its efficient implementation. Examples in wireless channel equalization and minimum-variance distortionless-response beamforming show that the backward selection algorithm yields optimally sparse designs in many instances while also highlighting the benefits of sparse design.

A 12b 1GS/s SiGe BiCMOS two-way time-interleaved pipeline ADC

Pipelined ADCs designed in analog BiCMOS technologies can offer good linearity and high SNR performance for input signals with reasonable voltage swings. Such ADCs, however, face two critical design challenges: the process limits the sampling rate, and the pipeline architecture limits power efficiency. This paper introduces a two-way time-interleaved (TI) switched-current 1Gs/s 12b pipelined ADC in SiGe BiCMOS that addresses these issues.

A 12 Bit 1.6 GS/s BiCMOS 2×2 Hierarchical Time-Interleaved Pipeline ADC

This paper describes a 12 bit 1.6 GS/s pipeline ADC realized in a 0.18 μm complementary BiCMOS SiGe process. The ADC consists of a four-way time-interleaved hierarchical structure and a master-slave T&H to improve the dynamic performance of the individual sub-ADCs and to reduce both the converter error rate and the complexity of the required interleaving background calibration algorithms. It achieves an SFDR of 79 dBc and 66 dBc at low and high frequency inputs, respectively and an error rate of less than 10-9, and has a power consumption of 1.15 W for the core ADC.

9.1 A 45nm CMOS RF-to-Bits LTE/WCDMA FDD/TDD 2×2 MIMO base-station transceiver SoC with 200MHz RF bandwidth

Increasing mobile data demands are pushing cellular network capacity. Massive MIMO base stations with large antenna arrays and smaller cell sizes demand higher integration in radio transceivers than what is available [1].

Performance comparison of TEQ design techniques for FDM ADSL

TEQ design to maximize the data rate for FDM ADSL channels is challenging due to the bandsplit filtering. In this paper, a performance comparison of several TEQ design techniques is presented for typical FDM channels. It is observed that (a) no single TEQ design criterion achieves the maximum performance, and (b) the performance is limited by the resulting TEQ design producing large variations in the passband region and/or emphasizing the stopband region. It is then shown that in many of these cases, better performance can be obtained by applying a spectral flatness constraint to the TEQ design. Additionally, we demonstrate that the dual TEQ and per tone equalizer are well suited to equalizing FDM ADSL systems.

A bit-constrained sar adc for compressive acquisition of frequency sparse signals

We introduce a novel analog-to-digital converter (ADC) based on the traditional successive approximation register. This architecture employs compressive sensing (CS) techniques to acquire and reconstruct frequency sparse signals. One important difference between our approach and traditional CS systems is that our architecture constrains the number of bits used during acquisition rather than the number of measurements. Our system is able to flexibly partition a fixed budget in order to trade the number of measurements it acquires with the quantization depth given to each measurement. We show that this degree of flexibility is particularly advantageous for ameliorating the CS noise folding phenomenon, allowing our ADC significant gains over measurement-constrained compressive sensing systems.

1.5mm precision liquid level measurement using impedance spectroscopy

An impedance measurement based level sensor is proposed using a co-axial probe for sensing liquid level in a container. The co-axial sensing probe is made with a hollow stainless steel outer conductor enclosing an insulated inner conductor. The impedance of the co-axial probe varies with the water level in a nonlinear fashion. The supporting electronics was developed using MSP 432 microcontroller unit (MCU) platform from Texas Instruments (TI) and a newly designed Impedance Analyzer-Analog Front End (IA-AFE) developed at TI. An inverter amplifier based circuit was implemented within the IA-AFE for impedance measurement. Discrete Fourier Transform (DFT) is calculated on the MCU platform from the sampled input and output square wave voltages of the IA-AFE. The proposed sensor shows a maximum error within ±1.5 mm, for the probe of length 40 cm. The proposed system offers an accurate and economical liquid level measurement platform outperforming the state-of-art level sensors to the best of our knowledge.

Joint TX and feedback RX IQ mismatch compensation for integrated direct conversion transmitters

The direct conversion (DC) architecture has been adopted for wireless base-station transceivers due to its cost and area efficiency. The shortcomings of DC transceivers need to be overcome to meet their high performance requirements. In-phase (I) and quadrature phase (Q) mismatch is one of most significant impairments. This paper presents an integrated, on-line mismatch compensation system which calibrates frequency-dependent transmitter (TX) and feedback receiver (FBRX) IQ mismatches using the digital TX signal as a reference. The proposed method was fabricated in 45nm CMOS technology. Measurements show 60 dBc TX ACPR for 20MHz LTE low-IF signals. TX EVM of 0.8% is achieved with 20MHz zero-IF LTE signals.

A 12 bit 1.6 GS/s BiCMOS 2×2 hierarchical time-interleaved pipeline ADC

A 12 bit 1.6 GS/s pipeline ADC realized in a 0.18 μm complementary BiCMOS SiGe process is presented. The ADC consists of a four-way time-interleaved hierarchical structure and a master-slave T/H to improve the dynamic performance of the individual sub-ADCs and to reduce both the complexity of the required interleaving background calibration algorithms and the error rate. It achieves an SFDR of 79 dBc at low frequency inputs and 66 dBc at Nyquist, and has an error rate of less than 10-9.