Huseyin Dinc

A 16-bit 250-MS/s IF Sampling Pipelined ADC With Background Calibration

This paper describes a 16-bit 250 MS/s ADC fabricated on a 0.18 BiCMOS process. The ADC has an integrated input buffer with a new linearization technique that improves its distortion by 5-10 dB and lowers its power consumption by 70% relative to the state of the art. It demonstrates a new background calibration technique to correct the residue amplifier (RA) gain errors and lower its power consumption. This summing node sampling (SNS) calibration technique is based on sampling the summing-node voltage of the residue amplifier and using it with the corresponding residue to estimate the amplifier open loop gain. The ADC achieves an SNDR of 76.5 dB and consumes 850 mW from a 1.8 V supply, while the input buffer consumes 150 mW from a 3 V supply. Up to 125 MS/s, the SFDR is greater than 100 dB for input frequencies up to 100 MHz and 90 dB up to 300 MHz input frequency. At 250 MS/s, the SFDR is greater than 95 dB up to 100MHz and 85 dB up to 300 MHz.

29.3 A 14b 1GS/s RF sampling pipelined ADC with background calibration

We describe a 14-bit 1GS/s pipelined ADC that relies on correlation-based background calibration to correct the inter-stage gain, settling (dynamic) and memory errors. An effective dithering technique is embedded in the calibration signal to break the dependence of the calibration on the input signal amplitude. In addition, to improve the sampling linearity, the ADC employs input distortion cancellation and another digital calibration to compensate for the non-linear charge injection (kickback) from the sampling capacitors on the input driver. The ADC is fabricated in a 65nm CMOS process and has an integrated input buffer. With a 140MHz and 2Vpp input signal, the SNR is 69dB, the SFDR is 86dB, and the power is 1.2W.

A 14-bit 2.5GS/s and 5GS/s RF sampling ADC with background calibration and dither

We describe a 14-bit 2.5GS/s non-interleaved pipelined ADC that relies on correlation-based background calibrations to correct the inter-stage gain, settling (dynamic), kick-back and memory errors. A new technique is employed to inject a large dither signal on the input to dither the non-linear kick-back on the ADC driver, and another large dither signal is injected to dither any residual non-linearity in the pipeline. In order to correct the effect of aging on the comparators, a new background calibration technique is employed to correct the comparator offsets. The ADC is fabricated as a dual in a 28nm CMOS process. An optional interleaved mode is provided, where the two ADCs on chip are time-interleaved to obtain a single 14-bit 5GS/s ADC. Background calibration of offset and gain mismatch and fixed calibration of timing mismatch between the two channels are implemented on chip.