Hyeokjae Lee

Analysis of body bias effect with PD-SOI for analog and RF applications

Abstract The interaction of the body bias effect, device size, and analog characteristics such as DC gain, the matching effect, and speed ( f T and f max ) of the sub-0.2 μm PD-SOI technology is reported. From the study, the optimized device size and the body bias for the analog and radio-frequency applications can be determined according to the specific utilization of the chip.

An anomalous device degradation of SOI narrow width devices caused by STI edge influence

The effects of shallow trench isolation (STI) on silicon-on-insulator (SOI) devices are investigated for various device sizes with three different gate shapes. Both NMOSFETs and PMOSFETs with the channel region butted to the STI show a reduction in mobility (NMOSFETs and PMOSFETs) and an increase of low-frequency noise as the channel width is reduced. In comparison, the devices without the STI-butted channel region show much less variation in mobility for various channel widths. The degradation of MOSFET yield in SOI MOSFETs with the STI is found to be dependent on the device width since the contribution of the interface roughness (or damage) between the STI and the channel formed during the dry etch process becomes significant with the decrease of channel width and the increase of channel length. From the charge-pumping results, the interface state (N/sub it/) generated by the STI process was identified as the cause of the anomalous degradation.

Accuracy of a proposed implant impression technique using abutments and metal framework

PURPOSE This study compared the accuracy of an abutment-framework (A-F) taken with open tray impression technique combining cementon crown abutments, a metal framework and resin cement to closed tray and resin-splinted open tray impression techniques for the 3-implant definitive casts. The effect of angulation on the accuracy of these 3 techniques was also evaluated. MATERIAL AND METHODS Three definitive casts, each with 3 linearly positioned implant analogs at relative angulations 0, 30, and 40 degrees, were fabricated with passively fitted corresponding reference frameworks. Ten impressions were made and poured, using each of the 3 techniques on each of the 3 definitive casts. To record the vertical gap between reference frameworks and analogs in duplicate casts, a light microscope with image processing was used. Data were analyzed by two-way analysis of variance and the Tukey test. RESULTS The open tray techniques showed significantly smaller vertical gaps compare to closed tray technique (P < .05). The closed tray and the resin-splinted open tray technique showed significantly different vertical gaps according to the angulation of implant (P < .05), but the A-F impression technique did not (P > .05). CONCLUSION The accuracy of the A-F impression technique was superior to that of conventional techniques, and was not affected by the angulation of the implants.

Effects of the dissolved oxygen in Ti films on Ti reactions in Cu/Ti/SiO2/Si system upon annealing

The reactions of Cu/Ti/SiO2 structures at temperatures ranging from 200 to 700 °C have been studied for various Ti thicknesses. X-ray and Rutherford backscattering spectroscopy (RBS) analyses were used to identify the reaction products resulting from Ti reactions in Cu/Ti/SiO2 systems and the oxygen composition in the unreacted Ti, and revealed a correlation between the oxygen concentration in Ti films and the sequences of the Ti reactions. The reaction products initially formed, at around 300 °C, were a series of Cu–Ti intermetallics (Cu3Ti/CuTi) at the Cu–Ti interface with the oxygen dissolved in the Ti moving from the compounds into the remaining unreacted Ti. At 500 °C, the Cu3Ti was converted into Cu-rich intermetallics, Cu4Ti, which grew at the expense of the CuTi due to the increased oxygen content in the Ti. In addition, the outdiffusion of Ti, to the Cu surface, and the Ti–SiO2 reactions caused an abrupt increase in the oxygen content in the Ti layer, which placed thermodynamic restraints on further Ti reactions. Furthermore, thinner Ti layers showed a higher increased rate of oxygen accumulation for the same consumption of Ti, which led to significantly reduced Ti consumption. The diffusion barrier properties of SiO2 for Cu metallization decreased with an increasing Ti thickness.

Low-frequency noise degradation caused by STI interface effects in SOI-MOSFETs

The low-frequency noise characteristics of SOI MOSFETs with shallow trench isolation (STI) structure are investigated for various device sizes with three different gate shapes. Devices with channel region butted to the STI show an increase of low-frequency noise as the channel width is reduced. In comparison, the devices without the STI butted to the channel region show much less increase of noise power spectral density with channel width. From the charge pumping and noise measurement results, the interface-state generated by the STI process is identified as the cause of these anomalous phenomena.

Enhancing leakage suppression in carbon-rich silicon junctions

Carbon-incorporated devices exhibit an increase in junction leakage relative to pure Si devices. The authors demonstrate that a leakage suppression of /spl sim/ 50 times can be achieved in carbon-rich (Si:C) junctions. This is accomplished by a prolonged annealing for 1 to 10 min at 850 /spl deg/C (much lower than typical annealing temperature of >1000/spl deg/C) and is attributed to a decrease in interstitial carbon concentration. After a 10-min annealing, the Si:C junctions display a leakage of 4/spl times/10/sup -13/ A//spl mu/m, which is much lower than that of 1050 /spl deg/C spike annealed Si junctions and well within the I/sub off/ requirements of low-standby-power device at the 45-nm node. Carbon-incorporated transistors with a gate length of 0.18 /spl mu/m exhibit an I/sub off/ reduction of /spl sim/ 10 times, compared to pure Si transistors, and both transistors have a similar subthreshold slope of 81 mV/dec.

Leakage suppression of gated diodes fabricated under low-temperature annealing with substitutional carbon Si/sub 1-y/C/sub y/ incorporation

We have demonstrated the fabrication of n/sup +/-p gated diodes using low-temperature annealing of 700/spl deg/C for 30 s with a significantly reduced junction leakage current. This is achieved with the incorporation of an epitaxially grown Si/sub 1-y/C/sub y/(y=0.0007) layer in the substrate located at the end-of-range (EOR) of arsenic implantations. The carbon devices show effectively suppressed EOR defects in the cross-sectional transmission electron microscopy images and leakage characteristics similar to the controlled silicon device fabricated under high-temperature annealing of 950/spl deg/C for 30 s. Arrhenius measurement of the leakage profiles has indicated identical leakage mechanism for both the pure silicon and carbon devices, thus signifying the substantial elimination of the secondary EOR defects resulted from the implantations despite the low-temperature annealing of the latter.

Time-Varying Body Instability and Low-Frequency Noise Characteristics of Mini-Field-Dual-Body Silicon-on-Insulator Structure for Analog-Digital Mixed-Mode Circuits

A new silicon-on-insulator (SOI) structure for analog-digital mixed applications was proposed where analog and digital metal oxide semiconductor field effect transistors (MOSFETs) are independently optimized. Two types of field oxide are introduced such that the body bias of analog devices can be effectively controlled whereas the channel region for digital devices is fully depleted without the increase of source/drain resistance. The AC body potential instability was investigated by measurements and modeling of the body-related device characteristics. In addition, low-frequency noise characteristics of analog MOSFETs with different body contact structures are shown and analyzed. It was shown that the proposed structure is a strong candidate for the future SOI technology applicable to analog-digital mixed-mode circuits.

A dual body SOI structure for mixed analog-digital mode circuits

A new silicon-on-insulator (SOI) structure for mixed analog-digital applications is proposed where analog and digital MOSFETs are independently optimized. Two types of field oxide are introduced so that the body bias of analog devices can be effectively controlled whereas the channel region for digital devices is fully depleted. From measurements of the body related device characteristics such as the output resistance, the variation of threshold voltage and transconductance, 1/f noise, body resistance, and the self-heating effect, it is shown that the proposed structure is promising for SOI technology in mixed analog-digital mode circuit applications.

An anomalous device degradation of SOI devices with STI

The degradation of the electrical characteristics of SOI MOSFETs with STI structure is found to be dependent on the device size. The degradation is due to decreased mobility in N/P MOSFETs caused by the interface roughness (or damage) between STI and channel formed during the dry etch process, and becomes significant with the decrease in channel width and increase in channel length. The magnitude of normalized mobility of wide channel devices is higher 25% than that of narrow channel devices. These phenomena are confirmed by device simulation.