J. G. Lee

Diffusion barrier and electrical characteristics of a self-aligned MgO layer obtained from a Cu(Mg) alloy film

Diffusion barrier characteristics and electrical properties of self-aligned MgO layers obtained from a Cu(Mg) alloy film have been investigated. Self-aligned surface and interfacial MgO layers were formed upon annealing a Cu(Mg) film in an oxygen ambient and prevented interdiffusion of Cu in SiO2 up to 700 °C. The thermal stability of a pure Cu/TiN/Si multilayer system has been significantly enhanced up to 800 °C by the MgO layers by forming a MgO/Cu/MgO/TiN/Si multilayer system. A combined structure of Si3N4(500 A)/MgO(100 A) increased the breakdown voltage up to 20 V from 15 V and reduced the leakage current density down to 3×10−9 A/cm2 from 1×10−8 A/cm2 compared to a pure copper system. Consequently, the deposition of Cu(Mg) alloy followed by annealing in an oxygen ambient gives rise to the formation of a self-aligned MgO layer with excellent diffusion barrier and electrical characteristics and the film can be applied as a gate electrode in thin-film transistor/liquid-crystal displays, resulting in a r...

A self-passivated Cu(Mg) gate electrode for an amorphous silicon thin-film transistor

The feasibility of using Cu(Mg) alloy film as a gate electrode for thin-film transistor (TFT) liquid crystal displays has been investigated. When pure Cu was used as a gate electrode, severe interdiffusion occurred between Cu and the gases SiH4, NH3, and CF4 during plasma-enhanced chemical vapor deposition of a gate dielectric, SiNx, and dry etching of the SiNx. On the other hand, the deposition of a Cu(Mg) alloy film gives rise to the formation of a MgO/Cu bilayer structure with low Cu resistivity, good adhesion to SiO2, higher leakage current density, and excellent passivation capability. A hydrogenated amorphous silicon TFT with a MgO encapsulated Cu gate exhibited a gate voltage swing of 0.91 V/dec. and a threshold voltage of 6.8 V, resulting in a reduction of process steps and better performance.

Highly Conformal Deposition of Pure Co Films by MOCVD Using Co2 ( CO ) 8 as a Precursor

Highly conformal Co thin films were deposited on SiO 2 trenches with an aspect ratio of 13 by metallorganic chemical vapor deposition (MOCVD) using Co 2 (CO) 8 as a precursor in a low-temperature regime of 50-70°C where the growth rate was 3.5-7.0 nm/min. Lowering the pressure of the process reduces the number of collisions in the gas phase and, thus, widens the temperature regime in which the surface reaction controls the growth rate. A processing pressure of 26.7 Pa (0.2 Torr) allows for conformal deposition only at 50°C, whereas deposition at a reduced pressure of 4.0 Pa (0.03 Torr) widens the temperature regime (50-70°C) in which excellent conformality can be obtained. The confonnal Co thin film, produced at 50°C and 4.0 Pa, showed a resistivity of 10-12 μΩ cm and contained 1.0 atom % oxygen and less than 1.0 atom % carbon. After annealing this film at 600°C, its resistivity was reduced to 6 μΩ cm, which is close to the bulk resistivity (5.7 μΩ cm) of Co. Therefore, this low-temperature process, which allows for the excellent conformal deposition of pure Co films, can be utilized to produce silicided contacts for advanced devices which require a low contact resistance and good electrical performance.

Stoichiometry dependence of electrochemical performance of thin-film SnOx microbattery anodes deposited by radio frequency magnetron sputtering

Thin-film SnOx microbattery anodes, with various oxygen deficiencies, are deposited from a SnO2 target on to an ambient temperature substrate by radio frequency (RF) magnetron sputtering. The high reversible capacity and cycle performance characteristics of SnOx are described. RF power density and process gas pressure during deposition are fixed at 2.5 W/cm2 and 10 mTorr, respectively. The SnOx films are characterized by energy dispersive X-ray spectroscopy (EDS), X-ray diffraction (XRD), and X-ray photoelectron spectroscopy (XPS). Constant-current galvanostatic charge–discharge tests of half cells are also performed. The stoichiometric parameter x increases with the increase in oxygen partial pressure, but decreases when the number of Sn chips placed on the target material in an argon atmosphere are increased. It is observed that SnOx transforms to lithium oxide and metallic Sn after an initial Li intercalation reaction. The charge–discharge performance of the tin oxide films is found to be dependent on stoichiometry. In the present work, SnO1.43 is the optimum stoichiometry, exhibiting the highest reversible capacity (498.33 μA h/cm2 μm) and the lowest irreversible capacity (301.79 μA h/cm2 μm).

Self-passivated copper as a gate electrode in a poly-Si thin film transistor liquid crystal display

Self-passivated copper as a gate electrode in the form of TiO/Cu/TiO/TiN/SiO2 has been obtained by annealing Cu/Ti/TiN/SiO2. The thickness of Ti in Cu/TiTiN was optimized at 150 A by forming an 80 A continuous TiO film on the outer surface of the Cu. The multilayer of SiO2/TiO/Cu/TiO/TiN/SiO2 showed stable electrical passivating properties against Cu diffusion into the top or bottom SiO2. Consequently, self-passivated copper has secured the dielectric properties of plasma enhanced chemical vapor deposition SiO2 and can be utilized as a gate electrode in low temperature poly-Si thin film transistor liquid crystal displays without sacrificing the low resistivity of Cu.

Pattern Recognition Using Carbon Nanotube Synaptic Transistors with an Adjustable Weight Update Protocol

Recent electronic applications require an efficient computing system that can perform data processing with limited energy consumption. Inspired by the massive parallelism of the human brain, a neuromorphic system (hardware neural network) may provide an efficient computing unit to perform such tasks as classification and recognition. However, the implementation of synaptic devices (i.e., the essential building blocks for emulating the functions of biological synapses) remains challenging due to their uncontrollable weight update protocol and corresponding uncertain effects on the operation of the system, which can lead to a bottleneck in the continuous design and optimization. Here, we demonstrate a synaptic transistor based on highly purified, preseparated 99% semiconducting carbon nanotubes, which can provide adjustable weight update linearity and variation margin. The pattern recognition efficacy is validated using a device-to-system level simulation framework. The enlarged margin rather than the linear weight update can enhance the fault tolerance of the recognition system, which improves the recognition accuracy.

Mechanism of surface modification of a porous-coated Ti-6Al-4V implant fabricated by electrical resistance sintering

A porous-coated Ti-6Al-4V implant was fabricated by electrical resistance sintering, using 480 μF capacitance and 1.5 kJ input energy. X-ray photoelectron spectroscopy (XPS) was used to study the surface characteristics of the implant material before and after sintering. There were substantial differences in the content of O and N between as-received atomized Ti-6Al-4V powders and the sintered prototype implant, which indicates that electrical resistance sintering alters the surface composition of Ti-6Al-4V. Whereas the surface of atomized Ti-6Al-4V powders was primarily TiO2, the surface of the implant consisted of a complex of titanium oxides as well as small amounts of titanium carbide and nitride. It is proposed that the electrical resistance sintering process consists of five stages: stage I – electronic breakdown of oxide film and heat accumulation at the metal-oxide interface; stage II – physical breakdown of oxide film; stage III – neck formation and neck growth; stage IV – oxidation, nitriding, and carburizing; and stage V – heat dissipation. The fourth stage, during which the alloy repassivates, is responsible for the altered surface composition of the implant.

Effects of molybdenum, silver dopants and a titanium substrate layer on copper film metallization

Annealing of 100 nm-thick Cu, Cu(Mo) and Cu(Ag) films was carried out to investigate the effect of dopant atoms on the films. Molybdenum (Mo) and silver (Ag) were selected as immiscible dopants for out-diffusion studies. A thermally grown SiO2 layer and a sputtered Ti layer were used as substrates. The dopant and substrate effects were characterized in terms of surface morphology, resistivity, preferred orientation, and diffusional characteristics. The lowest observed resistivity was 2.32 μΩ · cm in the Cu(Ag) film, which was lower than that in a pure Cu film of the same thickness. Ag addition enhanced the surface morphology and thermal stability of the Cu(Ag) films. The highest thermal stability was obtained in the case of a Cu(Mo)/Ti film which maintained film integrity to 800°C. A Ti substrate enhanced Cu(111) texture growth. A highly oriented Cu(111)-texture was obtained in the Cu(Mo)/Ti films. Cu diffusion through the Ti layer was limited in the (111)-textured Cu(Mo)/Ti films, which showed good potential as a diffusion barrier.

Logic circuits composed of flexible carbon nanotube thin-film transistor and ultra-thin polymer gate dielectric.

Printing electronics has become increasingly prominent in the field of electronic engineering because this method is highly efficient at producing flexible, low-cost and large-scale thin-film transistors. However, TFTs are typically constructed with rigid insulating layers consisting of oxides and nitrides that are brittle and require high processing temperatures, which can cause a number of problems when used in printed flexible TFTs. In this study, we address these issues and demonstrate a method of producing inkjet-printed TFTs that include an ultra-thin polymeric dielectric layer produced by initiated chemical vapor deposition (iCVD) at room temperature and highly purified 99.9% semiconducting carbon nanotubes. Our integrated approach enables the production of flexible logic circuits consisting of CNT-TFTs on a polyethersulfone (PES) substrate that have a high mobility (up to 9.76 cm2 V−1 sec−1), a low operating voltage (less than 4 V), a high current on/off ratio (3 × 104), and a total device yield of 90%. Thus, it should be emphasized that this study delineates a guideline for the feasibility of producing flexible CNT-TFT logic circuits with high performance based on a low-cost and simple fabrication process.

Fabrication of Cu/Co bilayer gate electrodes using selective chemical vapor deposition and soft lithographic patterning

A templated Cu/Co bilayer gate electrode was fabricated using the combined method of consecutive and selective chemical vapor deposition (CVD), and octadecyltrichlorosilane (OTS) microcontact printing techniques. Soft lithographically patterned self-assembled monolayers (SAMs) can direct the growth of Co occurring at the low temperatures 50–90 °C and serve as a template for the consecutive and selective growth of Cu, thereby forming stable and high quality Cu/Co bilayer gate electrodes on a glass substrate. This simple process provides fewer process steps and higher performance than other conventional processes, and can be applied to the fabrication of large area and high resolution thin film transistor liquid crystal displays.