Hyeong-Cheol Oh

A Low Hardware Cost 2D Vector Graphic Rendering Algorithm for Supersampling Antialiasing

An edge-flag rendering algorithm for supersampling antialiasing with low hardware cost is presented. The proposed algorithm works differently from the common rendering algorithm, using only one counter per pixel instead of one counter per sample point. Compared to the common rendering algorithm, the proposed one uses about 83% less memory capacity for a scanline-sized buffer and saves nearly 65% of the computation work performed in implementing the 8-Queen supersampling algorithm on XVGA panels. Experiments show that the proposed algorithm performs antialiasing with fairly good quality as well.

A low-power DSP-enhanced 32-bit EISC processor

EISC (Extendable Instruction Set Computer) is a compressed code architecture developed for embedded applications and has higher code density than its competing architectures. In this paper, we propose a low-power DSP-enhanced embedded microprocessor based on the 32-bit EISC architecture. We present how we could exploit the special features, and how we could overcome the deficits, of the EISC architecture to accelerate DSP applications while adding relatively low hardware overhead. Our simulation results show that the proposed DSP-enhanced processor reduces the execution time of the considered DSP kernels by 77.6% and the MP3 applications by 30.9%. The proposed DSP enhancements cost approximately 10300 gates (18%) and do not increase the clock frequency. While the high code density of EISC would be of great advantage to a low-power embedded system, the proposed DSP enhancement could increase its power consumption by 16.9%. We show that a set of supports for power management could reduce the power consumption by 65.5%. The proposed processor has been embedded in an SoC for video processing and proven in silicon.

Retiming for high speed and low power design

The positioning of flip-flops in a sequential circuit is related to the power dissipation as well as the clock period of the circuit. We show that genetic algorithms can be used to find efficiently the optimal positioning for the power performance of CMOS digital circuits without sacrificing the clock periods. As the result of evaluating our design method, we reduce dissipation of power about 9-10% with preserving optimal clock period.

Design of a Loeffler DCT using Xilinx Vivado HLS (Abstract Only)

Loeffler discrete cosine transform (DCT) algorithm is recognized as the most efficient one because it requires the theoretically least number of multiplications. However, many applications still encounter difficulty in performing the 11 multiplications required by the algorithm to calculate a 1D eight-point DCT. To avoid expensive multipliers in the hardware, we used two design methods, namely, distributed arithmetic (DA) and shift-and-add (SAA) methods, to design the DCT accelerator. The memory bandwidth is 60 bits: 24 bits for reads of the R(red), G(green), and B(blue) data of a pixel and 36 bits for writes of three corresponding 12-bit DCT coefficients. Thus, the 1D eight-point DCT accelerator for each of R, G, and B can have one 12-bit input port and one 12-bit output port so that it can calculate a 2D DCT by row-column decomposition method. The designs are adjusted to produce the same latency and interval. DA seems promising because Loeffler DCT requires only three small tables with four input bits. However, our experiments using Xilinx Vivado HLS show that the SAA design is better than the DA design for the considered applications. Furthermore, simulation results suggest that the optimal accelerator design can be obtained by adjusting the SAA design to the considered applications. The resultant SAA design requires only 13 adders (per color component) and can calculate one DCT coefficient per clock cycle. The precision of the internal hardware has been adjusted, such that the reconstructed images have PSNR values of at least 39.1 dB for all test images (Lenna, Pepper, House, and Cameraman). If a precision of 13bits is allowed, PSNR becomes at least 44.8 dB. Our presentation describes the architecture and operation of the optimized SAA design.

A DSP-enhanced 32-bit embedded microprocessor

EISC (Extendable Instruction Set Computer) is a compressed code architecture developed for embedded applications. In this paper, we propose a DSP-enhanced embedded microprocessor based on the 32-bit EISC architecture. We present how we could exploit the special features, and how we could overcome the weaknesses, of the EISC architecture to accelerate DSP applications with a relatively low hardware overhead. Our simulations and experiments show that the proposed DSP-enhanced processor reduces the average execution times of the DSP kernels and DSP applications considered in this work, by 42.5% and 31.3% respectively. The proposed DSP enhancements cost about 10300 gates and do not affect the operating frequency of the processor. The proposed DSP-enhanced processor has been embedded in an SoC for video processing and proven in silicon.

A DSP-Enhanced 32-bit embedded microprocessor

EISC (Extendable Instruction Set Computer) is a compres-breal sed code architecture developed for embedded applications. In this paper, we propose a DSP-enhanced embedded microprocessor based on the 32-bit EISC architecture. We present how we could exploit the special features, and how we could overcome the deficits, of the EISC architecture to accelerate DSP applications with a relatively low hardware overhead. Our simulations and experiments show that the proposed DSP-enhanced processor reduces the average execution time of the DSP kernels considered in this work by 47.8% and the DSP applications by 29.3%. The proposed DSP enhancements cost about 10300 gates and do not increase the clock frequency. The proposed DSP-enhanced processor has been embedded in an SoC for video processing and proven in silicon.

Efficient hardware multiplicative inverters

We propose two hardware inverters for calculating the multiplicative inverses in finite fields GF(2m): one produces a result in every O(m) time using O(m) area; and the other produces a result in every O(1) time using O(m2) area. While existing O(m)-time inverters require at least two shift registers in the datapath, the proposed O(m)-time implementation uses only one, thus costing less hardware. By exploiting the idea used in the O(m)-time inverter and developing a new way of controlling the dataflow, we also design a new O(1)-time inverter that works faster but costs less hardware than the best previously proposed O(1)-time implementation with the same area-time complexity.