Hyon-Goo Kang

Realization of vertical resistive memory (VRRAM) using cost effective 3D process

Vertical ReRAM (VRRAM) has been realized with modification of Vertical NAND (VNAND) process and architecture as a cost-effective and extensible technology for future mass data storage. Dedicated ALD/CVD deposition and wet etching processes were developed to reproduce planar ReRAM properties in VRRAM structure. Multi-stack of VRRAM cell layers were fabricated at the same time using ALD TaOx/barrier layer/CVD TiN cell stacks. Oxidation control without intermixing has been found very critical in the vertical ReRAM cell process.

Extended scalability of perpendicular STT-MRAM towards sub-20nm MTJ node

In this article, we report the first experimental demonstration of sub-20nm MTJ cells for investigating the downscaling feasibility of spin-transfer torque (STT) MRAM, one of the most promising candidates to replace conventional memories. We demonstrate the STT switching of 17nm node P-MTJ cells, the smallest feature size ever reported, utilizing perpendicular materials possessing high interface anisotropy of 2.5 erg/cm2 and improved integration processes to achieve reproducible switching with critical current (Ic) of 44uA, tunneling magneto-resistance (TMR) ratio of 70% and thermal stability factor (E/kBT) of 34.

PRAM cell technology and characterization in 20nm node size

We reported characteristics of 20nm PRAM cell. Optimization of diode integration process and improved implantation technology were used to satisfy the required diode on-current (Ion) with low off-current (Ioff). Confined cell structure and novel bottom electrode (BE) materials were developed to reduce a reset current (Ireset) below 100uA. Using the advanced technologies, we successfully produced fully integrated 20nm node size PRAM device for the first time.

Effect of polysilicon gate on the flatband voltage shift and mobility degradation for ALD-Al/sub 2/O/sub 3/ gate dielectric

Al/sub 2/O/sub 3/ (EOT=22.7 /spl Aring/) gate dielectric layer formed by Atomic Layer Deposition (ALD) process have been characterized for sub-100 nm CMOS devices. The gate leakage current was 3 orders of magnitude lower than that of SiO/sub 2/ and the hysteresis of C-V curve was not observed. However, the negative fixed charge induced the flat band voltage (Vfb) shift and degraded the channel mobility of MOS transistor. The Vfb shift was reduced and channel mobility was improved by applying P+ gate by BF/sub 2/ implantation. It is suggested that the phosphorous diffused from gate polysilicon has a role of network modifier in Al/sub 2/O/sub 3/ film and formation of the Al-O- dangling bond which may be ascribed to negative fixed charge.

A novel SiGe-inserted SOI structure for high performance PDSOI CMOSFETs

A novel partially-depleted silicon-on-insulator (PDSOI) CMOSFETs with SiGe-inserted layer have been proposed. The SiGe-inserted layer in NMOS successively suppresses the floating body effects (FBE) by lowering the body-to-source potential barrier to hole current. It also provides a good current performance in PMOS by inducing the change of channel dopant distribution and increasing the efficiency of pocket ion implantation. Consequently, SiGe-inserted SOI devices achieve higher drain-to-source breakdown voltage in NMOS due to the suppression of FBE and increase drive currents of both NMOS and PMOS by 10% and 15%, respectively, compared to conventional PDSOI devices.

Highly manufacturable SONOS non-volatile memory for the embedded SoC solution

A new Local SONOS structure has been proposed for an embedded NVM cell in 0.13 /spl mu/m standard CMOS logic process. The localized storage silicon nitride layer of Local SONOS cell provides the essential properties for the embedded NVM such as the complete erase, low program current, and high on cell current from the low threshold voltage. The entire embedded memory solution has been realized with 0.276 /spl mu/m/sup 2/ Local SONOS NVM cell, which has 20 /spl mu/s program and 2 ms erase speed under 5.5 V bias condition, and good reliability without the special algorithms and cell array modifications.

Stress minimization in deep sub-micron full CMOS devices by using an optimized combination of the trench filling CVD oxides

We have found that the defect generation which is induced by the mechanical stress during the densification, depends on the ratio of the trench filling material composed of the TEOS-O/sub 3/ based CVD oxide with tensile stress and the plasma enhanced CVD oxide with compressive stress. The lower as-deposited stress is, the lower the maximum stress during the densification is. This stress level is proportional to the defect density which is generated in fabricating MOSFETs with Shallow Trench Isolation (STI). In order to achieve devices without a defect, it is important to minimize as-deposited stress level by optimizing the ratio of the trench filling CVD oxides.

CMOS device scaling beyond 100 nm

CMOS device scaling beyond 100 nm has been investigated. Issues on scaling and previous works to solve them were reviewed. Super steep retrograde channel formation using selective epitaxial growth of undoped silicon effectively suppressed short channel effect and improved transconductance. The stack gate dielectrics of oxynitride and nitride suppressed boron penetration and improved drive currents. Transistor characteristics and reliability issues on gate oxide scaling were investigated in the regime of large gate leakage currents. High performance CMOS transistors of L/sub gate/=70 nm and T/sub ox/=1.4 nm were fabricated, which showed current drives of 860 /spl mu/A//spl mu/m (NMOS) and 350 /spl mu/A//spl mu/m (PMOS) at I/sub off/=10 nA//spl mu/m and V/sub dd/=1.2 V.

Manufacturable embedded CMOS 6T-SRAM technology with high-k gate dielectric device for system-on-chip applications

Manufacturable embedded CMOS 6T-SRAM with the HfO/sub 2/-Al/sub 2/O/sub 3/ dielectric for system-on-chip (SoC) applications is successfully demonstrated for the first time in the semiconductor industry. The possibility of the high-k gate dielectric in low power SoC applications is suggested. 0.11/spl mu/m NFET and PFET devices with thin high-k gate dielectric have 470 and 150/spl mu/A//spl mu/m at Ioff=0.1nA/um and Vdd=1.2V, respectively. Inversion thickness of NFET and PFET are 2.4nm and 2.7nm, respectively. Gate leakage current of the high-k is 1000 times lower than that of the oxynitride at the accumulation region. Static noise margin of 2.14/spl mu/m/sup 2/ 6T-SRAM bit cell is about 300mV at Vdd=1.2V. 6T-SRAM chip yield of the high-k is comparable to that of the oxynitride. The post nitridation after high-k film deposition is very important to the yield of the SRAM chips due to the suppression of the PFET boron penetration. Stand-by current of the SRAM chips with the high-k is shown to be a decreases of 60% compared with the oxynitride.

On the gate oxide scaling of high performance CMOS transistors

The gate oxide scalability of high performance CMOS transistor has been investigated. In terms of gate leakage, the T/sub ox/ can be scaled down to at least 8 /spl Aring/ with I/sub G/ not exceeding I/sub off/ limit suggested by ITRS. To reduce boron penetration, remote-plasma-nitridation (RPN) oxides were studied. Devices with RPN oxides showed excellent resistance against boron penetration, improved hole mobility, reduced gate leakage, and improved transistor performance. The gate oxide scalability can be extended using the RPN process.