N.I. Lee

Effect of polysilicon gate on the flatband voltage shift and mobility degradation for ALD-Al/sub 2/O/sub 3/ gate dielectric

Al/sub 2/O/sub 3/ (EOT=22.7 /spl Aring/) gate dielectric layer formed by Atomic Layer Deposition (ALD) process have been characterized for sub-100 nm CMOS devices. The gate leakage current was 3 orders of magnitude lower than that of SiO/sub 2/ and the hysteresis of C-V curve was not observed. However, the negative fixed charge induced the flat band voltage (Vfb) shift and degraded the channel mobility of MOS transistor. The Vfb shift was reduced and channel mobility was improved by applying P+ gate by BF/sub 2/ implantation. It is suggested that the phosphorous diffused from gate polysilicon has a role of network modifier in Al/sub 2/O/sub 3/ film and formation of the Al-O- dangling bond which may be ascribed to negative fixed charge.

A novel SiGe-inserted SOI structure for high performance PDSOI CMOSFETs

A novel partially-depleted silicon-on-insulator (PDSOI) CMOSFETs with SiGe-inserted layer have been proposed. The SiGe-inserted layer in NMOS successively suppresses the floating body effects (FBE) by lowering the body-to-source potential barrier to hole current. It also provides a good current performance in PMOS by inducing the change of channel dopant distribution and increasing the efficiency of pocket ion implantation. Consequently, SiGe-inserted SOI devices achieve higher drain-to-source breakdown voltage in NMOS due to the suppression of FBE and increase drive currents of both NMOS and PMOS by 10% and 15%, respectively, compared to conventional PDSOI devices.

Highly manufacturable SONOS non-volatile memory for the embedded SoC solution

A new Local SONOS structure has been proposed for an embedded NVM cell in 0.13 /spl mu/m standard CMOS logic process. The localized storage silicon nitride layer of Local SONOS cell provides the essential properties for the embedded NVM such as the complete erase, low program current, and high on cell current from the low threshold voltage. The entire embedded memory solution has been realized with 0.276 /spl mu/m/sup 2/ Local SONOS NVM cell, which has 20 /spl mu/s program and 2 ms erase speed under 5.5 V bias condition, and good reliability without the special algorithms and cell array modifications.

Manufacturable embedded CMOS 6T-SRAM technology with high-k gate dielectric device for system-on-chip applications

Manufacturable embedded CMOS 6T-SRAM with the HfO/sub 2/-Al/sub 2/O/sub 3/ dielectric for system-on-chip (SoC) applications is successfully demonstrated for the first time in the semiconductor industry. The possibility of the high-k gate dielectric in low power SoC applications is suggested. 0.11/spl mu/m NFET and PFET devices with thin high-k gate dielectric have 470 and 150/spl mu/A//spl mu/m at Ioff=0.1nA/um and Vdd=1.2V, respectively. Inversion thickness of NFET and PFET are 2.4nm and 2.7nm, respectively. Gate leakage current of the high-k is 1000 times lower than that of the oxynitride at the accumulation region. Static noise margin of 2.14/spl mu/m/sup 2/ 6T-SRAM bit cell is about 300mV at Vdd=1.2V. 6T-SRAM chip yield of the high-k is comparable to that of the oxynitride. The post nitridation after high-k film deposition is very important to the yield of the SRAM chips due to the suppression of the PFET boron penetration. Stand-by current of the SRAM chips with the high-k is shown to be a decreases of 60% compared with the oxynitride.

Si FinFET based 10nm technology with multi Vt gate stack for low power and high performance applications

10nm logic technology using Si FinFET is developed for low power and high performance applications. Power-speed gain of 27% compared to 14nm technology node was obtained using four key developments: 1) advanced gate stack engineering enabling 4 multi-Vt devices, 2) 3rd generation Fin technology, 3) highly doped source/drain (S/D), and 4) contact resistance optimization. CVD liner for BEOL process was also applied for better metal fill capability. Finally yield of the smallest ever SRAM with 0.04um2 SRAM bit-cell size was demonstrated.

MRAM with novel shaped cell using synthetic anti-ferromagnetic free layer

Magnetic random access memory (MRAM) with magnetic tunnel junction (MTJ) using synthetic anti-ferromagnetic (SAF) free layers of various shapes has been developed. SAF free layers show the predominance in the scalability compared with a conventional single free layer. It is also revealed that a novel shaped MTJ with a SAF free layer has a remarkably large writing margin.

50nm gate length logic technology with 9-layer Cu interconnects for 90nm node SoC applications

A 90 nm generation logic technology with Cu/low-k interconnects is reported. 50 nm transistors are employed using gate oxide 1.3 nm in thickness and operating at 1.0 V. High speed transistors have drive currents of 870 /spl mu/A/pm and 360 /spl mu/A//spl mu/m for NMOS and PMOS respectively, while generic transistors have currents of 640 /spl mu/A//spl mu/m and 260 /spl mu/A//spl mu/m respectively. Low power process using high-k gate dielectrics and SOI process are also provided in this technology. The low-k SiOC material with 2.9 in the k value is used for 9 layers of dual damascene Cu/low-k interconnects. The effective k (k/sub eff/) value of interconnect is about 3.6. Fully working 6-T SRAM cell with an area of 1.1 /spl mu/m/sup 2/ and SNM value of 330 mV is obtained. For MIM capacitor, voltage coefficient of capacitance is less than 20 ppm/V.

On the gate oxide scaling of high performance CMOS transistors

The gate oxide scalability of high performance CMOS transistor has been investigated. In terms of gate leakage, the T/sub ox/ can be scaled down to at least 8 /spl Aring/ with I/sub G/ not exceeding I/sub off/ limit suggested by ITRS. To reduce boron penetration, remote-plasma-nitridation (RPN) oxides were studied. Devices with RPN oxides showed excellent resistance against boron penetration, improved hole mobility, reduced gate leakage, and improved transistor performance. The gate oxide scalability can be extended using the RPN process.

Practical next generation solution for stand-alone and embedded DRAM capacitor

For the first time, MIS capacitors with HfO/sub 2/-Al/sub 2/O/sub 3/ laminate are successfully demonstrated. The effective oxide thickness (EOT) of 21 /spl Aring/ with an acceptably low leakage current has been achieved for a cylinder-type MIS capacitor. The EOT of 21 /spl Aring/ is the smallest value reported for MIS capacitors with TiN electrodes regardless of dielectric material. We have confirmed the feasibility of reducing EOT in spite of the simple process without a pre-deposition treatment. HfO/sub 2/-Al/sub 2/O/sub 3/ laminate is also useful for SIS capacitors and can satisfy the needs of MIM capacitors for the next generation without changing electrode material.

Thermally robust Ta-doped Ni SALICIDE process promising for sub-50 nm CMOSFETs

For sub-50 nm device application, Self-Aligned siLICIDE (SALICIDE) process by NiTa alloy has been developed for the first time. Use of NiTa-alloy makes nickel silicide on 50 nm gate thermally-robust up to 600/spl deg/C during device fabrication. NiTa SALICIDE process can also achieve excellent value and distribution of sheet resistance on 30 nm gate as well as low junction leakage current compared to Co SALICIDE. Furthermore, the drive current of PMOS is greatly increased. As a result, high-performance 90 nm MOSFETs is successfully integrated with NiTa SALICIDE process.